
R8C/3GM Group
17. Timer RA
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
17. Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
17.1
Overview
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6 the Specifications of Each Mode).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Timer RA contains the following five operating modes:
Timer mode:
The timer counts the internal count source.
Pulse output mode:
The timer counts the internal count source and outputs pulses which invert the
polarity by underflow of the timer.
Event counter mode:
The timer counts external pulses.
Pulse width measurement mode:
The timer measures the pulse width of an external pulse.
Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Figure 17.1
Timer RA Block Diagram
Table 17.1
Pin Configuration of Timer RA
Pin Name
Assigned Pin
I/O
Function
TRAIO
P1_5 or P1_7
I/O
Function differs according to the mode.
Refer to descriptions of individual modes
for details
TRAO
P3_7
Output
Bits TCK2 to TCK0
TMOD2 to TMOD0
= other than 010b
Counter
Reload
register
TRAPRE register
(prescaler)
Data bus
Timer RA interrupt
Write to TRAMR register
Write 1 to TSTOP bit
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
Toggle
flip-flop
Q
CLR
CK
TOENA bit
TRAO pin
TCSTF
bit
TMOD2 to TMOD0
= 011b or 100b
TMOD2 to TMOD0
= 010b
Polarity
switching
Digital
filter
Counter
Reload
register
TRA register
(timer)
Bits TIPF1 to TIPF0
= 01b
= 10b
f8
f1
= 11b
f32
Count control
circuit
TMOD2 to TMOD0 = 001b
TOPCR bit
Underflow signal
Measurement
completion signal
Bits TIPF1 to TIPF0
= other than
000b
= 00b
TEDGSEL = 1
TEDGSEL = 0
= 000b
= 001b
= 011b
f2
f8
f1
= 010b
fOCO
= 100b
fC32
Note:
1. Bits TRAIOSEL0 and TRAIOSEL1 in the TRASR register are used to select which pin is assigned.
Bits TIOGT1 to TIOGT0
= 01b
= 10b
Do not set
Event input always enabled
= 00b
Event enabled for “L” period of
TRCIOD (timer RC output)
= 110b
fC
TRAIO pin (1)
TCKCUT
bit