
R8C/3GM Group
9. Clock Generation Circuit
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
9.2.4
Oscillation Stop Detection Register (OCD)
Notes:
1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or low-
speed on-chip oscillator mode (XIN clock stops).
2. If the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator
on).
3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if XIN clock oscillation stop is detected
while bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains
unchanged even when set to 0 (XIN clock selected).
4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). In addition,
the OCD3 bit cannot be used to confirm whether the XIN clock oscillation is stable.
5. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
for the switching procedure when the XIN clock re-oscillates after detecting oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register.
9.2.5
High-Speed On-Chip Oscillator Control Register 7 (FRA7)
Address 000Ch
Bit
b7b6b5
b4b3b2
b1b0
Symbol
After Reset
000
001
00
Bit
Symbol
Bit Name
Function
R/W
b0
OCD0
Oscillation stop detection enable bit
(7) 0: Oscillation stop detection function disabled
(1)1: Oscillation stop detection function enabled
R/W
b1
OCD1
Oscillation stop detection interrupt
enable bit
1: Enabled
R/W
b2
OCD2
System clock select bit
(3)0: XIN clock selected
(6)1: On-chip oscillator clock selected
(2)R/W
b3
OCD3
0: XIN clock oscillates
1: XIN clock stops
R
b4
—
Reserved bits
Set to 0.
R/W
b5
—
b6
—
b7
—
Address 0015h
Bit
b7b6b5
b4b3b2
b1b0
Symbol
——
———
After Reset
When shipping
Bit
Function
R/W
b7-b0 32 MHz frequency correction data is stored.
The frequency can be adjusted by transferring this value to the FRA3 register and by
transferring the correction value in the FRA6 register to the FRA1 register.
R