
R8C/3GM Group
34. Usage Notes
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
34.2.5
Rewriting Interrupt Control Register
(a) The contents of the interrupt control register can be rewritten only while no interrupt requests
corresponding to that register are generated. If an interrupt request may be generated, disable the interrupt
before rewriting the contents of the interrupt control register.
(b) When rewriting the contents of the interrupt control register after disabling the interrupt, be careful to
choose appropriate instructions.
Changing any bit other than the IR bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one
of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET.
Changing the IR bit
Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested).
Use the MOV instruction to set the IR bit to 0.
(c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to
(b) regarding rewriting the contents of interrupt control registers using the sample programs.
Examples 1 to 3 show how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of
the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer.
Example 1:
Use the NOP instructions to pause program until the interrupt control register is rewritten
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B
#00H,0056H
; Set the TRAIC register to 00h
NOP
;
NOP
FSET
I
; Enable interrupts
Example 2:
Use a dummy read to delay the FSET instruction
INT_SWITCH2:
FCLR
I
; Disable interrupts
AND.B
#00H,0056H
; Set the TRAIC register to 00h
MOV.W MEM,R0
; Dummy read
FSET
I
; Enable interrupts
Example 3:
Use the POPC instruction to change the I flag
INT_SWITCH3:
PUSHC
FLG
FCLR
I
; Disable interrupts
AND.B
#00H,0056H
; Set the TRAIC register to 00h
POPC
FLG
; Enable interrupts