
R8C/3GM Group
29. Comparator A
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
29.2.5
Voltage Monitor 1 Circuit Control Register (VW1C)
Notes:
1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit enabled).
Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (comparator A1 circuit disabled). To set the
2. When using the digital filter (while the VW1C1 bit is 0), set the CM14 bit in the CM1 register to 0 (low-speed on-
chip oscillator on).
To use the comparator A1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter
disabled).
3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit
enabled).
4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged
even if 1 is written to it).
5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the
VCAC1 bit to 0, set the VW1C7 bit.
6. When the VW1C0 bit is set to 1 (enabled), do not set the VW1C1 bit and bits VW1F1 and VW1F0 simultaneously
(with one instruction).
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW1C register.
Rewriting the VW1C register may set the VW1C2 bit to 1. After rewriting this register, set the VW1C2 bit to 0.
Address 0039h
Bit
b7b6
b5b4b3b2
b1
b0
Symbol
After Reset
1
000
1010
Bit
Symbol
Bit Name
Function
R/W
b0
VW1C0 Comparator A1 interrupt enable bit
(1) 0: Disabled
1: Enabled
R/W
b1
VW1C1 Comparator A1 digital filter
disable mode select bit
(2, 6)0: Digital filter enable mode
(digital filter circuit enabled)
1: Digital filter disable mode
(digital filter circuit disabled)
R/W
b2
VW1C2 Comparator A1 interrupt flag
(3, 4)[Condition to set this bit to 0]
0 is written.
[Condition to set this bit to 1]
When an interrupt request is generated.
R/W
b3
VW1C3 Comparator A1 signal monitor flag (3) 0: LVCMP1 < reference voltage 1: LVCMP1
≥ reference voltage
or comparator A1 circuit disabled
R
b4
VW1F0
Sampling clock select bit
(6)b5 b4
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
R/W
b5
VW1F1
R/W
b6
—
Reserved bit
Set to 0.
R/W
b7
VW1C7 Comparator A1 interrupt
generation condition select bit
(5)0: When LVCMP1 reaches reference voltage
or above.
1: When LVCMP1 reaches reference voltage
or below.
R/W