
R8C/3GM Group
22. Serial Interface (UART2)
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
Figure 22.3
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
D0 D1 D2 D3 D4 D5 D6 D7
TC
TCLK
Pulsing stops because TE bit is set to 0.
Data is set in U2TB register.
Data transfer from U2TB register to UART2 transmit register
TC = TCLK = 2(n+1)/fj
fj: Frequency of U2BRG count source
(f1, f8, f32, fC)
n: Setting value in U2BRG register
Transfer clock
TE bit in
U2C1 register
TI bit in
U2C1 register
CLK2
TXD2
TXEPT flag in
U2C0 register
CTS2
IR bit in
S2TIC register
Set to 0 when an interrupt request is acknowledged or by a program.
Pulsing stops because “H” is applied
to CTS2.
1/fEXT
Dummy data is set in U2TB register.
CLK2
RXD2
RTS2
RE bit in
U2C1 register
Data transfer from U2TB register to UART2 transmit register
Data read from U2RB register
fEXT: Frequency of external clock
Make sure the following conditions are met
when the CLK2 pin input before receiving data is high:
TE bit in U2C0 register = 1 (transmission enabled)
RE bit in U2C1 register = 1 (reception enabled)
Dummy data is written to U2TB register
Data transfer from UART2 receive
register to U2RB register
Set to 0 when an interrupt request is acknowledged or by a program.
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
D7
D6
TE bit in
U2C1 register
TI bit in
U2C1 register
OER flag in
U2RB register
IR bit in
S2RIC register
RI bit in
U2C1 register
The above applies when:
CKDIR bit in U2MR register = 0 (internal clock)
CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
The above applies when:
CKDIR bit in U2MR register = 1 (external clock)
CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
Received data taken in
“L” is applied when U2RB register is read.
(1) Transmit Timing Example (Internal Clock Selected)
(2) Receive Timing Example (External Clock Selected)