
R8C/3GM Group
31. Flash Memory
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
31.4.2
Flash Memory Control Register 0 (FMR0)
Notes:
1. To set this bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between writing 0
and writing 1.
2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is
set to 1 (CPU rewrite mode enabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in
the FST register is set to 1 (ready).
3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the
FST register is set to 0 (busy).
4. To set the FMR01 bit to 0 (CPU rewrite mode disabled), set it when the RDYSTI bit in the FST register is set to 0
(no flash ready status interrupt request) and the BSYAEI bit is set to 0 (no flash access error interrupt request).
FMR01 Bit (CPU Rewrite Mode Select Bit)
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software
commands.
FMR02 Bit (EW1 Mode Select Bit)
When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected.
Address 01B4h
Bit
b7b6b5b4b3b2b1b0
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
—
Reserved bit
Set to 0.
R/W
b1
FMR01
CPU rewrite mode select bit
(1, 4)0: CPU rewrite mode disabled
1: CPU rewrite mode enabled
R/W
b2
FMR02
0: EW0 mode
1: EW1 mode
R/W
b3
FMSTP
Flash memory stop bit
(2)0: Flash memory operates
1: Flash memory stops
(Low-power consumption state, flash memory
initialization)
R/W
b4
CMDRST Erase/write sequence reset bit
(3)When the CMDRST bit is set to 1, the erase/write
sequence is reset and erasure/writing can be
forcibly stopped.
When read, the content is 0.
R/W
b5
CMDERIE Erase/write error interrupt enable bit
0: Erase/write error interrupt disabled
1: Erase/write error interrupt enabled
R/W
b6
BSYAEIE Flash access error interrupt enable bit 0: Flash access error interrupt disabled
1: Flash access error interrupt enabled
R/W
b7
RDYSTIE Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled
1: Flash ready status interrupt enabled
R/W