
R8C/3GM Group
34. Usage Notes
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
When the stop condition (the SDA rising edge when SCL is high) is input, the BBSY bit becomes 0.
When writing 1 to the BBSY bit, 0 to the SCP bit, and the start condition (the SDA falling edge when SCL is
high) is output while SCL and SDA are high in master transmit mode, the BBSY bit becomes 1.
When writing 0 to bits BBSY and SCP, the stop condition (the SDA rising edge when SCL is high) is output
while SDA is low, and this is the only module that holds SCL low in master transmit mode or master receive
mode, the BBSY bit becomes 0.
When writing 1 to the FS bit in the SAR register, the BBSY bit becomes 0.
34.13.2.3 Additional Descriptions Regarding the IICRST Bit
When writing 1 to the IICRST bit, bits SDAO and SCLO in the ICCR2 register become 1.
When writing 1 to the IICRST bit in master transmit mode and slave transmit mode, the TDRE bit in the ICSR
register becomes 1.
While the control block of the I2C bus interface is reset by setting the IICRST bit to 1, writing to bits BBSY,
SCP, and SDAO is disabled. Write 0 to the IICRST bit before writing to the BBSY bit, SCP bit, or SDAO bit.
Even when writing 1 to the IICRST bit, the BBSY bit does not become 0. However, the stop condition (the
SDA rising edge when SCL is high) may be generated depending on the states of SCL and SDA and the
BBSY bit may become 0. There may also be a similar effect on other bits.
While the control block of the I2C bus interface is reset by setting the IICRST bit to 1, data transmission/
reception is stopped. However, the function to detect the start condition, stop condition, or arbitration lost
operates. The values in the ICCR1 register, ICCR2 register, or ICSR register may be updated depending on
the signals applied to pins SCL and SDA.
34.14 Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
34.15 Notes on A/D Converter
Write to the ADMOD register, the ADINSEL register, the ADCON0 register (other than ADST bit), the
ADCON1 register, the OCVREFCR register when A/D conversion is stopped (before a trigger occurs).
To use the A/D converter in repeat mode 0, repeat mode 1, or repeat sweep mode, select the frequency of the A/D
converter operating clock
φAD or more for the CPU clock during A/D conversion.
Do not select fOCO-F as
φAD.
Connect 0.1 F capacitor between the VREF pin and AVSS pin.
Do not enter stop mode during A/D conversion.
Do not enter wait mode during A/D conversion regardless of the state of the CM02 bit in the CM0 register (1:
Peripheral function clock stops in wait mode or 0: Peripheral function clock does not stop in wait mode).
Do not set the FMSTP bit in the FMR0 register to 1 (flash memory stops) during A/D conversion.
Do not change the CKS2 bit in the ADMOD register while fOCO-F is stopped.
During an A/D conversion operation, if the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops)
by a program to forcibly terminate A/D conversion, the conversion result of the A/D converter is undefined and
no interrupt is generated. The value of the ADi register before A/D conversion may also be undefined.
If the ADST bit is set to 0 by a program, do not use the value of all the ADi register.