
R8C/3GM Group
31. Flash Memory
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
31.4
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the software command only to blocks in the user ROM area.
The flash module has an erase-suspend function which halts the erase operation temporarily during an erase
operation in CPU rewrite mode. During erase-suspend, the flash memory can be read or programmed.
Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode.
Table 31.3
Differences between EW0 Mode and EW1 Mode
Item
EW0 Mode
EW1 Mode
Operating mode
Single-chip mode
Rewrite control program
allocatable area
User ROM
Rewrite control program
executable areas
RAM (The rewrite control program must
be transferred before being executed.)
However, the program can be executed
in the program ROM area when rewriting
the data flash area.
User ROM or RAM
Rewritable area
User ROM
However, blocks which contain the
rewrite control program are excluded.
Software command
restrictions
—
Program and block erase commands
Cannot be executed to any block which
contains the rewrite control program.
Mode after programming or
block erasure or after
entering erase-suspend
Read array mode
CPU state during
programming and
block erasure
The CPU operates.
The CPU operates while the data flash
area is being programmed or block
erased.
The CPU is put in a hold state while the
program ROM area is being programmed
or block erased. (I/O ports retain the state
before the command execution).
Flash memory
status detection
Read bits FST7, FST5, and FST4 in
the FST register by a program.
Read bits FST7, FST5, and FST4 in
the FST register by a program.
Conditions for entering
erase-suspend
Set bits FMR20 and FMR21 in the
FMR2 register to 1 by a program.
Set bits FMR20 and FMR22 in the
FMR2 register to 1 and the enabled
maskable interrupt is generated.
Set bits FMR20 and FMR21 in the FMR2
register to 1 by a program (while rewriting
the data flash area).
Set bits FMR20 and FMR22 in the FMR2
register to 1 and the enabled maskable
interrupt is generated.
CPU clock
Max. 20 MHz