
R8C/3GM Group
34. Usage Notes
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
34. Usage Notes
34.1
Notes on Clock Generation Circuit
34.1.1
Stop Mode
To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least four NOP instructions following the JMP.B instruction after the instruction which sets the CM10
bit to 1.
Program example to enter stop mode
BCLR
1,FMR0
; CPU rewrite mode disabled
BCLR
7,FMR2
; Low-current-consumption read mode disabled
BSET
0,PRCR
; Writing to CM1 register enabled
FSET
I
; Interrupt enabled
BSET
0,CM1
; Stop mode
JMP.B
LABEL_001
LABEL_001:
NOP
34.1.2
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
FMR27 bit to 0 (low-current-consumption read mode disabled) before entering the mode. Do not enter wait
mode while the FMR01 bit is 1 (CPU rewrite mode enabled) or the FMR27 bit is 1 (low-current-consumption
read mode enabled).
To enter wait mode by setting the CM30 bit to 1, set the I flag to 0 (maskable interrupt disabled).
To enter wait mode using the WAIT instruction, set the I flag to 1 (maskable interrupt enabled). An instruction
queue pre-reads 4 bytes from the instruction to set the CM30 bit to 1 (MCU enters wait mode) or the WAIT
instruction, and then the program stops. Insert at least four NOP instructions after the instruction to set the
CM30 bit to 1 (MCU enters wait mode) or the WAIT instruction.
Program example to execute the WAIT instruction
BCLR
1,FMR0
; CPU rewrite mode disabled
BCLR
7,FMR2
; Low-current-consumption read mode disabled
FSET
I
; Interrupt enabled
WAIT
; Wait mode
NOP
Program example to execute the instruction to set the CM30 bit to 1
BCLR
1, FMR0
; CPU rewrite mode disabled
BCLR
7, FMR2
; Low-current-consumption read mode disabled
BSET
0, PRCR
; Writing to CM3 register enabled
FCLR
I
; Interrupt disabled
BSET
0, CM3
; Wait mode
NOP
BCLR
0, PRCR
; Writing to CM3 register disabled
FSET
I
; Interrupt enabled