
R8C/3GM Group
29. Comparator A
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
29.2.6
Voltage Monitor 2 Circuit Control Register (VW2C)
Notes:
1. The VW2C0 is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled).
Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (comparator A2 circuit disabled). To set the
2. When using the digital filter (while the VW2C1 bit is 0), set the CM14 bit in the CM1 register to 0 (low-speed on-
chip oscillator on).
To use the comparator A2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter
disabled).
3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled).
4. Set this bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if
1 is written to it).
5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the
VCAC2 bit to 0, set the VW2C7 bit.
6. When the VW2C0 bit is set to 1 (enabled), do not set the VW2C1 bit and bits VW2F1 and VW2F0 simultaneously
(with one instruction).
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register.
Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0.
Address 003Ah
Bit
b7b6
b5b4b3b2
b1
b0
Symbol
After Reset
1
000
0010
Bit
Symbol
Bit Name
Function
R/W
b0
VW2C0
Comparator A2 interrupt enable bit
(1)0: Disabled
1: Enabled
R/W
b1
VW2C1
Comparator A2 digital filter disable mode
0: Digital filter enable mode
(digital filter circuit enabled)
1: Digital filter disable mode
(digital filter circuit disabled)
R/W
b2
VW2C2
Comparator A2 interrupt flag
(3, 4)[Condition to set this bit to 0]
0 is written.
[Condition to set this bit to 1]
When an interrupt request is generated.
R/W
b3
VW2C3
WDT detection monitor flag
(4)0: Not detected
1: Detected
R/W
b4
VW2F0
Sampling clock select bit
(6)b5 b4
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
R/W
b5
VW2F1
R/W
b6
VW2C6
Reserved bit
Set to 0.
R/W
b7
VW2C7
Comparator A2 interrupt
generation condition select bit
(5)0: When LVCMP2 reaches reference voltage
or above.
1: When LVCMP2 reaches reference voltage
or below.
R/W