
R8C/3GM Group
22. Serial Interface (UART2)
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
22.4
Clock Asynchronous Serial I/O (UART) Mode
In UART mode, data is transmitted and received after setting the desired bit rate and transfer data format.
TableNotes:
1. If an overrun error occurs, the receive data in the U2RB register will be undefined.
2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART2 receive
register to the U2RB register.
Table 22.5
UART Mode Specifications
Item
Specification
Transfer data format
Character bits (transfer data): Selectable from 7, 8, or 9 bits
Start bit:1 bit
Parity bit: Selectable from odd, even, or none
Stop bits: Selectable from 1 bit or 2 bits
Transfer clock
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1))
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
fEXT: Input from CLK2 pin n: Setting value in the U2BRG register: 00h to FFh
Transmit/receive control
Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
Transmit start conditions
To start transmission, the following requirements must be met:
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
If the CTS function is selected, input to the CTS2 pin = “L”.
Receive start conditions
To start reception, the following requirements must be met:
The RE bit in the U2C1 register is set to 1 (reception enabled).
Start bit detection
Interrupt request generation
timing
For transmission, one of the following conditions can be selected.
The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
The U2IRS bit is set to 1 (transmission completed):
When data transmission from the UART2 transmit register is completed.
For reception
When data is transferred from the UART2 receive register to the U2RB register
(at completion of reception).
Error detection
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the bit one before the last stop bit of the
next unit of data.
This error occurs when the set number of stop bits is not detected.
This error occurs when if parity is enabled, the number of 1’s in the parity and
character bits does not match the set number of 1’s.
Error sum flag
This flag is set to 1 if an overrun, framing, or parity error occurs.
Selectable functions
LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be
selected.
Serial data logic switching
This function inverts the logic of the transmit/receive data. The start and stop bits
are not inverted.
TXD, RXD I/O polarity switching
This function inverts the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data are inverted.
RXD2 digital filter selection
The RXD2 input signal can be enabled or disabled.