
R8C/3GM Group
19. Timer RC
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
19.6
PWM Mode
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register
is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.)
PWM Mode.
j = B, C, or D
h = A, B, C, or D
Table 19.11
Specifications of PWM Mode
Item
Specification
Count source
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
External signal (rising edge) input to TRCCLK pin
Count operation
Increment
PWM waveform
PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive level width: 1/fk × (n + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
Count start condition
1 (count starts) is written to the TSTART bit in the TRCMR register.
Count stop condition
When the CSEL bit in the TRCCR2 register is set to 0 (count continues
after compare match with TRCGRA).
0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at
compare match with TRCGRA register).
The count stops at the compare match with the TRCGRA register. The
PWM output pin retains the level after the output is changed by the
compare match.
Interrupt request generation
timing
Compare match (contents of registers TRC and TRCGRh match)
The TRC register overflows.
TRCIOA pin function
Programmable I/O port
TRCIOB, TRCIOC, and
TRCIOD pin functions
Programmable I/O port or PWM output (selectable individually for each
pin)
INT0 pin function
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer
The count value can be read by reading the TRC register.
Write to timer
The TRC register can be written to.
Selectable functions
One to three pins selectable as PWM output pins
One or more of pins TRCIOB, TRCIOC, and TRCIOD
Active level selectable for each pin
Initial level selectable for each pin
A/D trigger generation
m+1
n+1
m-n
(Active level is “L”)