
R8C/3GM Group
25. I2C bus Interface
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
25.2.10 IIC bus Status Register (ICSR)
Notes:
1. Each bit is set to 0 by reading 1 before writing 0.
2. This flag is enabled in slave receive mode with the I2C bus format.
3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface
monitors the SDA pin and the data which the I2C bus Interface transmits is different, the AL flag is set to 1 and
the bus is occupied by another master.
4. The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit
is set to 1, transfer is halted).
5. The RDRF bit is set to 0 when data is read from the ICDRR register.
6. Bits TEND and TDRE are set to 0 when data is written to the ICDRT register.
When reading these bits immediately after writing to the ICDRT register, insert three or more NOP instructions
between the instructions used for writing and reading.
7. When writing 0 to the ICE bit in the ICCR1 register or 1 to the IICRST bit in the ICCR2 register during an I2C bus
interface operation, the BBSY bit in the ICCR2 register and the STOP bit may become undefined. Refer to 25.9 When accessing the ICSR register continuously, insert one or more NOP instructions between the instructions
to access it.
Address 019Ch
Bit
b7b6b5
b4b3b2
b1b0
Symbol
After Reset
000
0
X
0
Bit
Symbol
Bit Name
Function
R/W
b0
ADZ
General call address
This flag is set to 1 when a general call address is detected.
R/W
b1
AAS
Slave address
This flag is set to 1 when the first frame immediately after the
start condition matches bits SVA0 to SVA6 in the SAR register
in slave receive mode (slave address detection and general call
address detection)
R/W
b2
AL
Arbitration lost flag/
I2C bus format:
This flag indicates that arbitration has been lost
in master mode.
This flag is set to 1
(3) when:
The internal SDA signal and SDA pin level do not match at
the rising edge of the SCL signal in master transmit mode
The SDA pin is held “H” at start condition detection in master
transmit/receive mode
Clock synchronous format:
This flag indicates an overrun error.
This flag is set to 1 when:
The last bit of the next unit of data is received
while the RDRF bit is set to 1
R/W
b3
STOP
Stop condition detection
This flag is set to 1 when a stop condition is detected after the
frame is transferred.
R/W
b4
NACKF No acknowledge
This flag is set to 1 when no ACKnowledge is detected from the
receive device after transmission.
R/W
b5
RDRF
Receive data register
This flag is set to 1 when receive data is transferred from
registers ICDRS to ICDRR.
R/W
b6
TEND
I2C bus format:
This flag is set to 1 at the rising edge of the 9th clock cycle of
the SCL signal while the TDRE bit is set to 1.
Clock synchronous format:
This flag is set to 1 when the last bit of the transmit frame is
transmitted.
R/W
b7
TDRE
Transmit data empty flag
This flag is set to 1 when:
Data is transferred from registers ICDRT to ICDRS and the
ICDRT register is empty
The TRS bit in the ICCR1 register is set to 1 (transmit mode)
A start condition is generated (including retransmission)
Slave receive mode is changed to slave transmit mode
R/W