參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 78/141頁
文件大?。?/td> 2027K
代理商： 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 78 of 134
38D5 Group
Software Commands
Table 18 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, execute a
software command to specify an erase or program operation.
Each software command is explained below.
Read Array Command (FF
16
)
The read array mode is entered by writing the command code
“FF
16
” in the first bus cycle. When an address to be read is input
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D
0
to D
7
).
The read array mode is retained until another command is
written.
Read Status Register Command (70
16
)
When the command code “70
16
” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D
0
to D
7
) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (50
16
)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that
operation has ended in an error. To use this command, write the
command code “50
16
” in the first bus cycle.
Program Command (40
16
)
Program operation starts when the command code “40
16
” is
written in the first bus cycle. Then, if the address and data to
program are written in the 2nd bus cycle, program operation
(data programming and verification) will start.
Whether the write operation is completed can be confirmed by
read status register or the RY/BY status flag. To read the status
register, write the read status register command “70
16
”. The
status register bit 7 (SR7) is set to “0” at the same time the
program starts and returned to “1” upon completion of the
program. The read status mode remains active until the read
array command (“FF
16
”) is written.
The RY/BY status flag is set to “0” during program operation
and “1” when the program operation is completed as is the status
register bit 7 (SR7).
At program end, program results can be checked by reading the
status register.
Fig 75. Program flowchart
NOTES:
1. SRD = Status Register Data
2. WA = Write Address, WD = Write Data
3. BA = Block Address to be erased (Input the maximum address of each block.)
4. X denotes a given address in the User ROM area.
Start
Write “40
16
”
SR7 =
“
1
”
or
RY/BY =
“
1
”
Read status register
Program completed
NO
YES
Write
Write address
Write data
SR4 = “0”
Program error
NO
YES
Table 18
List of software commands (CPU rewrite mode)
Command
cycle
number
First bus cycle
Second bus cycle
Mode
Address
Data
(D
0
to D
7
)
FF
16
70
16
50
16
40
16
20
16
Mode
Address
Data
(D
0
to D
7
)
Read array
Read status register
Clear status register
Program
Block erase
1
2
1
2
2
Write
Write
Write
Write
Write
X
(4)
X
X
X
X
Read
X
SRD
(1)
Write
Write
WA
(2)
BA
(3)
WD
(2)
D0
16
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