參數(shù)資料
型號(hào)： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 51/141頁(yè)
文件大小： 2027K
代理商： 38D5
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 51 of 134
38D5 Group
LCD DRIVE CONTROL CIRCUIT
The 38D5 Group has the built-in Liquid Crystal Display (LCD)
drive control circuit consisting of the following.
LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 36 segment output pins and 8 common output
pins can be used.
Up to 256 pixels can be controlled for an LCD display. When the
LCD enable bit is set to “1” after data is set in the LCD mode
register, the segment output disable register, and the LCD display
RAM, the LCD drive control circuit starts reading the display
data automatically, performs the bias control and the duty ratio
control, and displays the data on the LCD panel.
.
Table 12
Fig. 43 Structure of LCD related registers
Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixels
36 dots
or 8 segment LCD 4 digits
72 dots
or 8 segment LCD 9 digits
108 dots
or 8 segment LCD 13 digits
144 dots
or 8 segment LCD 18 digits
256 dots
or 8 segment LCD 32 digits
1
2
3
4
8
LCD mode register 1
(LM 1 : address 0013
16
)
b7
b0
Duty ratio selection bits
b2b1b0
0 0 0 : 1 (Static)
0 0 1 : 2 (use COM
0
, COM
1
)
0 1 0 : 3 (use COM
0
-COM
2
)
0 1 1 : 4 (use COM
0
-COM
3
)
1 0 0 to 1 1 0 : Not available
1 1 1 : 8 (COM
0
-COM
7
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit
0 : f(X
CIN
)/32
1 :
SOURCE/8192
LCD mode register 2
(LM2 : address 0014
16
)
b7
b0
Voltage multiplier circuit control bit
0 : Voltage multiplier circuit disabled
(Input ports P7
0
/INT
01
, P7
1
/INT
11
)
1 : Voltage multiplier circuit enabled (C
1
, C
2
pins)
V
L3
connection bit
0 : Connect LCD internal V
L3
to V
CC
1 : Connect LCD internal V
L3 to
V
L3
pin
Not used (returns “0” when read)
Segment output disable register 0
(SEG0 : address 0FF4
16
)
b7
b0
Segment output disable bit 0
0 : Segment output SEG
8
1 : Output port P0
0
Segment output disable bit 1
0 : Segment output SEG
9
1 : Output port P0
1
Segment output disable bit 2
0 : Segment output SEG
10
1 : Output port P0
2
Segment output disable bit 3
0 : Segment output SEG
11
1 : Output port P0
3
Segment output disable bit 4
0 : Segment output SEG
12
1 : Output port P0
4
Segment output disable bit 5
0 : Segment output SEG
13
1 : Output port P0
5
Segment output disable bit 6
0 : Segment output SEG
14
1 : Output port P0
6
Segment output disable bit 7
0 : Segment output SEG
15
1 : Output port P0
7
Segment output disable register 1
(SEG1 : address 0FE5
16
)
b7
b0
Segment output disable bit 8
0 : Segment output SEG
0
1 : Output port P2
0
Segment output disable bit 9
0 : Segment output SEG
1
1 : Output port P2
1
Segment output disable bit 10
0 : Segment output SEG
2
1 : Output port P2
2
Segment output disable bit 11
0 : Segment output SEG
3
1 : Output port P2
3
Segment output disable bit 12
0 : Segment output SEG
4
1 : Output port P2
4
Segment output disable bit 13
0 : Segment output SEG
5
1 : Output port P2
5
Segment output disable bit 14
0 : Segment output SEG
6
1 : Output port P2
6
Segment output disable bit 15
0 : Segment output SEG
7
1 : Output port P2
7
Notes 1
: When “1” is selected as duty ratio by the duty ratio selection bits,
set “1” to the bias control bit.
2
: LCDCK is a clock for the LCD timing controller.
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
3
: Only pins set to output ports by the direction register can be controlled
to switch to output ports or segment outputs by the segment output
disable register.
4
: When disabling the voltage multiplier circuit, the C
1
and C
2
pins
function as input ports P7
0
/INT
01
, P7
1
/INT
11
.
Segment output disable register 2
(SEG2 : address 0FF6
16
)
b7
b0
Segment output disable bit 16
0 : Segment output SEG
16-
SEG
19
1 : Output port P1
0-
P1
3
Segment output disable bit 17
0 : Segment output SEG
20-
SEG
23
1 : Output port P1
4-
P1
7
Segment output disable bit 18
0 : Segment output SEG
24-
SEG
27
1 : Output port P3
0-
P3
3
Segment output disable bit 19
0 : Segment output SEG
28-
SEG
31
1 : Output port P3
4-
P3
7
Not used (do not write “1”)
(1)
(2)
(4)
(3)
(3)
(3)
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