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| 型號： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 42/141頁 |
| 文件大小： | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 42 of 134
38D5 Group
<Notes on Timer Y>
CNTR
1
Interrupt Active Edge Selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit. However, in pulse width HL continuously
measurement mode, CNTR
1
interrupt request is generated at
both rising and falling edges of CNTR
1
pin input signal
regardless of the setting of CNTR
1
active edge switch bit.
Timer Y Read/Write Control
When reading from/writing to timer Y, read from/write to both
the high-order and low-order bytes of timer Y. When the value
is read, read the high-order bytes first and the low-order bytes
next. When the value is written, write the low-order bytes first
and the high-order bytes next.
Write to or read from the timer Y register by the 16-bit unit. If
reading from the timer Y register during write operation or
writing to it during read operation is performed, normal
operation will not be performed.
Which write control can be selected by the timer Y write
control bit (b0) of the timer Y control register (address
0039
16
), writing data to both the latch and the timer at the
same time or writing data only to the latch. When writing a
value to the timer Y address to write to the latch only, the value
is set into the reload latch and the timer is updated at the next
underflow. After reset release, when writing a value to the
timer Y address, the value is set into the timer and the timer
latch at the same time, because they are set to write at the same
time.
When writing to the latch only, if the write timing to the high-
order reload latch and the underflow timing are almost the
same, the value is set into the timer and the timer latch at the
same time. In this time, counting is stopped during writing to
the high-order reload latch.
Switch the frequency division or count source* while the timer
count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-chip
oscillator mode, XIN mode, or low-speed mode). Be careful
when changing settings in the CPU mode register.
Fig. 32 Structure of Timer Y related registers
b7
b0
Timer Y control register
(TYCON: address 0039
16
)
Timer Y write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer Y count source selection bit
0 : Frequency divider output
1 : f(X
CIN
)
Timer Y frequency division selection bits
b3 b2
0 0 : 1/16
×
φ
SOURCE
0 1 : 1/1
×
φ
SOURCE
1 0 : 1/2
×
φ
SOURCE
1 1 : 1/256
×
φ
SOURCE
Not used (returns “0” when read)
Real time port 1 control bit (P5
0
)
0 : Real time port function invalid
1 : Real time port function valid
Real time port 2 control bit (P5
1
)
0 : Real time port function invalid
1 : Real time port function valid
RTP
0
data for real time port
RTP
1
data for real time port
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuous measurement mode
CNTR
1
active edge switch bit
0 : Count at rising edge in event counter mode
Measure falling period in period measurement mode
Falling edge active for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure rising period in period measurement mode
Rising edge active for CNTR
1
interrupt
Timer Y count stop bit
0 : Count operation
1 : Count stop
Timer Y mode register
(TYM: address 0038
16
)
b0
b7
Note1:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
Internal on-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)
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