Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 62 of 134
38D5 Group
CLOCK GENERATING CIRCUIT
The oscillation circuit of 38D5 Group can be formed by
connecting an oscillator, capacitor and resistor between X
IN
and
X
OUT
(X
CIN
and X
COUT
). To supply a clock signal externally,
input it to the X
IN
pin and make the X
OUT
pin open. The clocks
that are externally generated cannot be directly input to X
CIN
.
Use the circuit constants in accordance with the oscillator
manufacturer's recommended values. No external resistor is
needed between X
IN
and X
OUT
since a feed-back resistor exists
on-chip. (An external feed-back resistor may be needed
depending on conditions.) However, an about 10 M
external
feedback resistor is needed between X
CIN
and X
COUT
.
The 38D5 Group operation mode immediately after reset
depends on the OSCSEL pin state in the QzROM version.
When the OSCSEL pin state is GND level, the only on-chip
oscillator starts oscillating. The X
IN
-X
OUT
oscillation stops
oscillating, and X
CIN
and X
COUT
pins function as I/O ports.
Flash memory version as same.
When the OSCSEL pin state is V
CC
level, the X
IN
-X
OUT
oscillation divided by 8 starts oscillating. The on-chip oscillator
stops oscillating, and the X
CIN
and X
COUT
pins function as I/O
ports.
Note the following in each mode.
X
IN
Mode
The X
IN
-X
OUT
oscillation does not stop even if the X
IN
-X
OUT
oscillation stop bit is set to “1”.
Low-Speed Mode
The X
CIN
-X
COUT
oscillation stops if the port X
C
switch bit is set
to “0”.
On-Chip Oscillator Mode
Even if the on-chip oscillator stop bit is set to “1”, the on-chip
oscillator oscillation does not stop in the flash memory version,
but stops in the QzROM version.
Frequency Control
(1) On-chip oscillation mode
The system clock
φ
is the on-chip oscillator oscillation divided
by 32.
(2) X
IN
mode
Frequency/2 mode, frequency /4 mode, and frequency/8 mode
are collectively referred as X
IN
mode.
- Frequency/8 Mode
The system clock
φ
is the frequency of X
IN
divided by 8.
- Frequency/4 Mode
The system clock
φ
is the frequency of X
IN
divided by 4.
- Frequency/2 Mode
The system clock
φ
is half the frequency of X
IN
.
(3)Low-speed Mode
The system clock
φ
is half the frequency of sub clock.
After reset and when system returns from the stop mode, the
operation mode depends on the OSCSEL pin state in the
QzROM version and the flash memory version operation mode is
the on-chip oscillator mode.
When the RESET pin changes from “L” to “H” and when the
STP instruction is executed, determine the input level applied to
the OSCSEL pin.
Refer to the clock state transition diagram for the setting of
transition to each mode.
The X
IN
-
OUT
oscillation is controlled by the bit 5 of CPUM, and
the sub-clock oscillation is controlled by the bit 4 of CPUM and
the on-chip oscillator oscillation is controlled by the bit 0 of
CPUM2.
In the on-chip oscillator mode, the oscillation by the oscillator
can be stopped. In the low-speed mode, the power consumption
can be reduced by stopping the X
IN
X
OUT
oscillation.
In low-speed mode, the on-chip oscillator stops in the QzROM
version regardless of the on-chip oscillator stop bit value. The
on-chip oscillator does not stop in the flash memory version, so
set the on-chip oscillator stop bit to “1” to stop the oscillation.
Set enough time for oscillation to stabilize by programming to
restart the stopped oscillation and switch the operation mode.
Also, set enough time for oscillation to stabilize by programming
to switch the timer count source.
<Notes on Clock Generating Circuit>
If you switch the mode between on-chip oscillator mode, X
IN
mode and low-speed mode, stabilize both X
IN
and X
CIN
oscillations. Especially be careful immediately after power-on
and at returning from stop mode. Refer to the clock state
transition diagram for the setting of transition to each mode. Set
the frequency in the condition that f(X
IN
) > 3
f(X
CIN
).
When the X
IN
mode is not used (X
IN
-X
OUT
oscillation and
external clock input are not performed), connect X
IN
to V
CC
through a resistor.