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參數(shù)資料
| 型號： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 31/141頁 |
| 文件大?。?/td> | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 31 of 134
38D5 Group
<Notes>
The interrupt request bit may be set to “1” in the following cases.
When setting the external interrupt active edge
Related bits: INT
0
interrupt edge selection bit
(bit 0 of interrupt edge selection register
(address 003A
16
))
INT
1
interrupt edge selection bit
(bit 1 of interrupt edge selection register)
INT
2
interrupt edge selection bit
(bit 2 of interrupt edge selection register)
CNTR
0
activate edge switch bit
(bits 6 and 7 of timer X control register 1
(address 002E
16
))
CNTR
1
activate edge switch bit
(bits 6 of timer Y mode register
(address 0038
16
))
When switching the interrupt sources of an interrupt vector
address where two or more interrupt sources are assigned
Related bit:
Timer Y/CNTR
1
interrupt switch bit
(bit 3 of interrupt edge selection register)
When switching the INT pins
Related bits: INT
0
input port switch bit
(bit 4 of interrupt edge selection register)
INT
1
input port switch bit
(bit 5 of interrupt edge selection register)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Fig. 22 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
T1
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last
φ
cycle during one instruction cycle.
IR1T2
SYNC
IR2T3
1
2
Internal clock
φ
Instruction cycle
Push onto stack
Vector fetch
Instruction cycle
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