Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 54 of 134
38D5 Group
LCD Display RAM
The 36-byte area of address 0840
16
to 0863
16
is the designated
RAM for the LCD display. When “1” is written to these
addresses, the corresponding segments of the LCD display panel
are turned on.
The LCDCK timing frequency (LCD drive timing) is generated
internally and the frame frequency can be determined with the
following equation;
f(LCDCK)=
Frame frequency=
<Notes>
(1) Executing STP Instruction
Executing the STP instruction sets the LCD enable bit (bit 4 of
LCD mode register1 (address 0013
16
)) to “0” and the LCD panel
turns off. To turn the LCD panel on after returning from stop
mode, set the LCD enable bit to “1”.
(2) V
L3
Pin
To use the LCD drive control circuit while V
L3
is set to the
voltage equal to V
CC
, apply the V
CC
voltage to the V
L3
pin and
write “1” to the V
L3
connection bit (bit 1 of LCD mode register 2
(address 0014
16
)).
Fig. 46 LCD display RAM map
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)
duty ratio
Bits
Address
0840
16
0841
16
0842
16
0843
16
0844
16
0845
16
0846
16
0847
16
0848
16
0849
16
084A
16
084B
16
084C
16
084D
16
084E
16
084F
16
0850
16
0851
16
0852
16
0853
16
0854
16
0855
16
0856
16
0857
16
0858
16
0859
16
085A
16
085B
16
085C
16
085D
16
085E
16
085F
16
0860
16
0861
16
0862
16
0863
16
SEG
0
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
SEG
7
SEG
8
SEG
9
SEG
10
SEG
11
SEG
12
SEG
13
SEG
14
SEG
15
SEG
16
SEG
17
SEG
18
SEG
19
SEG
20
SEG
21
SEG
22
SEG
23
SEG
24
SEG
25
SEG
26
SEG
27
SEG
28
SEG
29
SEG
30
SEG
31
SEG
32
SEG
33
SEG
34
SEG
35
7
6
5
4
3
2
1
0
COM
3
COM
2
COM
1
COM
0
Bits
Address
0840
16
0841
16
0842
16
0843
16
0844
16
0845
16
0846
16
0847
16
0848
16
0849
16
084A
16
084B
16
084C
16
084D
16
084E
16
084F
16
0850
16
0851
16
0852
16
0853
16
0854
16
0855
16
0856
16
0857
16
0858
16
0859
16
085A
16
085B
16
085C
16
085D
16
085E
16
085F
16
0860
16
0861
16
0862
16
0863
16
SEG
0
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
SEG
7
SEG
8
SEG
9
SEG
10
SEG
11
SEG
12
SEG
13
SEG
14
SEG
15
SEG
16
SEG
17
SEG
18
SEG
19
SEG
20
SEG
21
SEG
22
SEG
23
SEG
24
SEG
25
SEG
26
SEG
27
SEG
28
SEG
29
SEG
30
SEG
31
7
6
5
4
3
2
1
0
COM
3
COM
2
COM
1
COM
0
COM
7
COM
6
COM
5
COM
4
Not used
(This area can be used as normal RAM.)
Not used
(This area can be used
as normal RAM.)
at 4COM
×
36SEG
at 8COM
×
32SEG