參數(shù)資料
型號: 38D5
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 13/141頁
文件大?。?/td> 2027K
代理商: 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 13 of 134
38D5 Group
Fig. 7 Register push and pop at interrupt generation and subroutine call
Interrupt request
On-going Routine
M(S)
(PC
H
)
(S)
(S)
1
M(S)
(PC
L
)
(S)
(S)
1
.
Execute RTS
Subroutine
(S)
(S) + 1
(PC
L
)
M(S)
(S)
(S) + 1
(PC
H
)
M(S)
M(S)
(PC
H
)
(S)
(S)
1
M(S)
(PC
L
)
(S)
(S)
1
M(S)
(PS)
(S)
(S)
1
Interrupt Service
Routine
(S)
(S)
+
1
(PS)
M(S)
(S)
(S)
+
1
(PC
L
)
M(S)
(S)
(S)
+
1
(PC
H
)
M(S)
Execute JSR
Execute RTI
(1)
Push return address
on stack
Push contents of processor
status register on stack
I Flag is set from “0” to “1”
Fetch the jump vector
POP contents of
processor status
register from stack
POP return
address
from stack
POP return address
from stack
Push return address
on stack
Note1
: Condition for acceptance of an interrupt request here
Interrupt disable flag is “0” and
Interrupt enable bit corresponding to each interrupt source is “1”
-
Table 7
Push and pop instructions of accumulator or processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Accumulator
Processor status register
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