參數資料
型號: 38D5
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數: 116/141頁
文件大?。?/td> 2027K
代理商: 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 116 of 134
38D5 Group
NOTE:
1. When bit 6 of address 001A
16
is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A
16
is “0” (UART).
Table 46
Timing requirements (2)
(V
CC
= 2.7 to 4.0 V, V
SS
= 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
2
125
Typ.
Max.
t
W
(RESET)
t
C
(X
IN
)
Reset input “L” pulse width
Main clock input cycle time
(X
IN
input)
μ
s
ns
t
WH
(X
IN
)
Main clock input “H” pulse width
50
ns
t
WL
(X
IN
)
Main clock input “L” pulse width
50
ns
t
C
(CNTR)
CNTR
0
, CNTR
1
input cycle time
1000/V
CC
ns
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(R
X
D-S
CLK1
)
t
h
(S
CLK1
-R
X
D)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
IN2
-S
CLK2
)
t
h
(S
CLK2
-S
IN2
)
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
00
, INT
01
, INT
10
, INT
11
, INT
2
input “H” pulse width
INT
00
, INT
01
, INT
10
, INT
11
, INT
2
input “L” pulse width
Serial I/O1 clock input cycle time
Serial I/O1 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
tc(CNTR)/2
20
tc(CNTR)/2
20
230
230
2000
950
950
400
200
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLASH MEMORY VERSION
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