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參數(shù)資料
| 型號(hào)： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 49/141頁 |
| 文件大?。?/td> | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 49 of 134
38D5 Group
A/D CONVERTER
The 38D5 Group has a 10-bit A/D converter. The A/D converter
performs successive approximation conversion. The 38D5 Group
has the ADKEY function which perform A/D conversion of the
“L” level analog input from the ADKEY pin automatically.
[AD Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the AD conversion register (high-order) (address
0017
16
), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the AD conversion register (low-order) (address
0016
16
).
During A/D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference
voltage input pin (V
REF
) can be controlled by the V
REF
input
switch bit (bit 0 of address 0016
16
). When “1” is written to this
bit, the resistor ladder is always connected to V
REF
. When “0” is
written to this bit, the resistor ladder is disconnected from V
REF
except during the A/D conversion.
[AD Control Register (ADCON)]
This register controls A/D converter. Bits 2 to 0 are analog input
pin selection bits. Bit 3 is an AD conversion completion bit and
“0” during A/D conversion. This bit is set to “1” upon
completion of A/D conversion.
A/D conversion is started by setting “0” in this bit.
Bit 5 is the ADKEY enable bit. The ADKEY function is enabled
by setting “1” to this bit. When this function is valid, the analog
input pin selection bits are ignored. Also, when bit 5 is “1”, do
not set “0” to bit 3 by program.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P5
7
/AN
7
P5
0
/AN
0
and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compare an analog input
voltage with the comparison voltage and store the result in the
AD conversion register. When an A/D conversion is completed,
the control circuit sets the AD conversion completion bit and the
AD conversion interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The
conversion accuracy may be low because the change is lost if the
conversion speed is not enough.
Accordingly, set f(X
IN
) to at least 500 kHz during A/D
conversion in the X
IN
mode.
Also, do not execute the STP and WIT instructions during the
A/D conversion.
In the low-speed mode and on-chip oscillator mode, there is no
limit on the oscillation frequency because the on-chip oscillator
is used as the A/D conversion clock. In the low-speed mode, on-
chip oscillator starts oscillation automatically at the A/D
conversion is executed and stops oscillation automatically at the
A/D conversion is finished even though it is not oscillating.
Fig. 41 Block diagram of A/D converter
(Address 0017
16
)
(Address 0016
16
)
ADKEY
control circuit
AV
SS
b7
b0
AD conversion register (L)
Data bus
C
AD conversion register (H)
Resistor ladder
Comparator
A/D interrupt request
AD control register
P5
0
/AN
0
P5
1
/AN
1
P5
2
/AN
2
P5
3
/AN
3
P5
4
/AN
4
P5
5
/AN
5
P5
6
/AN
6
P5
7
/AN
7
/ADKEY
0
V
REF
1/8
1/2
φ
SOURCE
Note 1:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the low-speed and the on-chip oscillator mode
A/D control circuit
(1)
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