參數(shù)資料
型號: 38D5
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 104/141頁
文件大小: 2027K
代理商: 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 104 of 134
38D5 Group
Timing Requirements And Switching Characteristics
NOTES:
1. 80 ns in the frequency/2 mode.
2. 32 ns in the frequency/2 mode.
3. When bit 6 of address 001A
16
is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A
16
is “0” (UART).
Table 31
Timing requirements (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Unit
Min.
2
62.5
125
25
50
25
50
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Max.
t
W
(RESET)
t
C
(X
IN
)
Reset input “L” pulse width
Main clock input cycle time
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
(1)
4.0V
V
CC
<
4.5V
4.5V
V
CC
5.5V
(2)
4.0V
V
CC
<
4.5V
4.5V
V
CC
5.5V
(2)
4.0V
V
CC
<
4.5V
t
WH
(X
IN
)
Main clock input “H” pulse
width
t
WL
(X
IN
)
Main clock input “L” pulse
width
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(R
X
D-S
CLK1
) Serial I/O1 input setup time
th(S
CLK1-
R
X
D)
Serial I/O1 input hold time
t
C
(S
CLK2
)
Serial I/O2 clock input cycle time
t
WH
(S
CLK2
)
Serial I/O2 clock input
“H”
pulse width
t
WL
(S
CLK2
)
Serial I/O2 clock input
“L”
pulse width
t
su
(S
IN2
-S
CLK2
)
Serial I/O2 input setup time
t
h
(S
CLK2
-S
IN2
)
Serial I/O2 input hold time
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input
“H”
pulse width
CNTR
0
, CNTR
1
input
“L”
pulse width
INT
00
, INT
01
, INT
10
, INT
11
, INT
2
input
“H”
pulse width
INT
00
, INT
01
, INT
10
, INT
11
, INT
2
input
“L”
pulse width
Serial I/O1 clock input cycle time
(3)
Serial I/O1 clock input “H” pulse width
(3)
Serial I/O1 clock input
“L”
pulse width
(3)
QzROM VERSION
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