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| 型號(hào)： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 127/141頁(yè) |
| 文件大小： | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 127 of 134
38D5 Group
Notes on Serial I/O1
1. Write to Baud Rate Generator
Write to the baud rate generator while transmission/reception is
stopped.
2. Setting Sequence When Serial I/O1 Transmit
Interrupt Used
To use the serial I/O1 transmit interrupt, if the interrupt
occurrence synchronized with settings is not required, take the
following sequence:
(1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of
interrupt control register 2 (address 003F
16
)) to “0”
(disabled).
(2) Set the transmit enable bit to “1”.
(3) After one or more instructions have been executed, set the
serial I/O1 transmit interrupt request bit (bit 2 of interrupt
request register 2 (address 003D
16
)) to “0” (no interrupt).
(4) Set the serial I/O1 transmit interrupt enable bit to “1”
(enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag (bit 0 of serial I/O1 status register) and the transmit
shift completion flag are set to “1”.
This allows an interrupt request to be generated regardless of
which interrupt occurrence source has been selected by the
transmit interrupt source selection bit (bit 3 of serial I/O1 control
register) and the serial I/O1 transmit interrupt request bit is set to
“1”.
3. Data Transmission Control Using Transmit Shift
Completion Flag
After transmit data is written to the transmit buffer register, the
transmit shift completion flag (bit 2 of serial I/O1 status register
(address 0019
16
)) changes from “1” to “0” after a delay of 0.5 to
1.5 cycles of the system clock. Thus, after transmit data is written
to the transmit buffer register, note this delay when controlling
data transmission by referencing the transmit shift completion
flag.
4. Setting Serial I/O1 Control Register
Before setting the serial I/O1 control register again, first set both
the transmit enable bit and the receive enable bit to “0” and
initialize the transmission and reception circuits.
Fig. 104 Sequence of setting serial I/O1 control register
5. Pin Status After Transmission Completed
After transmission is completed, the TxD pin retains the level
when transmission is completed.
When the internal clock is selected in clock synchronous serial
I/O mode, the S
CLK1
pin is set to “H”.
6. Serial I/O1 Enable Bit during Transmit Operation
During transmission, if the serial I/O1 enable bit (bit 7 of serial
I/O1 control register (address 001A
16
)) is set to “0”, the pin
function is set to an I/O port and the internal transmit operation
continues even though transmit data is not output externally.
Also, if the transmit buffer register is written in this state,
transmit operation starts internally. If the serial I/O1 enable bit is
set to “1” at this time, transmit data is output to the TxD pin from
that point.
7. Transmission
Selected
During data transmission, if the external clock is selected as the
synchronous clock, set the transmit enable bit to “1” while S
CLK1
is set to “H”. Also, write to the transmit buffer register while
S
CLK1
is set to “H”.
Control
When
External
Clock
8. Receive Operation in Clock Synchronous Serial I/O
Mode
During reception in clock synchronous serial I/O mode, set both
the transmit enable bit and the receive enable bit to “1”. Then
write dummy data to the transmit buffer register. When the
internal clock is selected as the synchronous clock, the
synchronous clock is output at this point and receive operation
starts. When the external clock is selected, reception is enabled at
this point and inputting the external clock starts transmit
operation.
The P4
1
/TxD pin outputs dummy data written in the transmit
buffer register.
9. Transmit/Receive Operation in Clock Synchronous
Serial I/O Mode
In clock synchronous serial I/O mode, set the transmit enable bit
and the receive enable bit to “0” simultaneously to stop
transmit/receive operations. If only one of the operations is
stopped, transmission and reception cannot be synchronized,
which will cause a bit error.
Notes on Serial I/O2
1. Switching Synchronous Clock
If the synchronous clock is switched by the serial I/O2
synchronous clock selection bit (bit 6 of serial I/O2 control
register (address 001D
16
)), initialize the serial I/O2 counter
(writing to serial I/O2 register (address 001F
16
)).
2. Notes When External Clock Selected
When the external clock is selected as the synchronous clock, the
S
OUT2
pin retains the D
7
level after transfer is completed.
However, if the synchronous clock is continuously input, the
serial I/O2 register continues shifting and the S
OUT2
pin keeps
outputting transmit data.
Also, write to the serial I/O2 register while S
CLK2
is set to “H”.
When the internal clock is selected as the synchronous clock, the
S
OUT2
pin is placed in the high-impedance state after transfer is
completed.
Set bits 0 to 3, and 6 of the serial I/O1 control
register.
Set both the transmit enable bit (TE) and the
receive enable bit (RE) to “0”
Set both the transmit enable bit (TE) and the receive
enable bit (RE), or one of them to “1”.
Settings can be made with
the LDM instruction at the
same time
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