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| 型號(hào)： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 126/141頁(yè) |
| 文件大?。?/td> | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 126 of 134
38D5 Group
10.Write to Timer X
(1) Timer X can select either writing data to both the latch and
the timer at the same time or writing data only by the timer
X write control bit (b3) in the timer X mode register
(address 002D
16
). When writing to the latch only, if a value
is written to the timer X address, the value is set into the
reload latch and the timer is updated at the next underflow.
After a reset release, if a value is written to the timer X
address, the value is set into the timer and the timer latch at
the same time, because they are written simultaneously.
When writing to the latch only, if the write timing to the
high-order reload latch and the underflow timing are almost
the same, the value is set into the timer and the timer latch at
the same time. At this time, count is stopped during write
operation to the high-order reload latch.
(2) Write to the timer X register by the 16-bit unit. Do not read
the timer X register while write operation is performed. If
the write operation is not completed, normal operation will
not be performed.
(3) Switch the frequency division or count source* while the
timer count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-
chip oscillator mode, X
IN
mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
11. Setting Timer X Mode Register
When PWM mode or IGBT output mode is set, be sure to set the
write control bit in the timer X mode register to “1” (writing to
latch only). After writing to the timer X register (high-order), the
contents of both registers are simultaneously reflected in the
output waveform at the next underflow.
12.Timer X Output Control Functions
To use the output control functions (INT
1
and INT
2
), set the
levels of INT
1
and INT
2
to “H” for the falling edge active or to
“L” for the rising edge active before switching to IGBT output
mode.
13.CNTR
0
Active Edge Selection
(1) Setting the CNTR
0
active edge switch bits also affects the
interrupt active edge at the same time.
(2) When the pulse width is measured, set bit 7 of the CNTR
0
active edge switch bits to “0”.
14.When Timer X Pulse Width Measurement Mode
Used
When timer X pulse mode measurement mode is used, enable the
event counter wind control data (bit 5 of timer X mode register
(address 002D
16
)) by setting to “0”.
<Reason>
If the event counter window control data (bit 5 of timer X mode
register (address 002D
16
)) is set to “1” (disabled) to
enable/disable the CNTR
0
input, the input is not accepted after
the timer 1 underflow.
15.CNTR1 Active Edge Selection
Setting the CNTR
1
active edge switch bits also affects the
interrupt active edge at the same time.
However, in pulse width HL continuous HL measurement mode,
the CNTR
1
interrupt request is generated at both rising and
falling edges of the pin regardless of the settings of the CNTR
1
active edge switch bits.
16.Read from/Write to Timer Y
(1) When reading from/writing to timer Y, read from/write to
both the high-order and low-order bytes of timer Y. To read
the value, read the high-order bytes first and the low-order
bytes next. To write the value, write the low-order bytes first
and the high-order bytes next.
Writing/reading should be preformed in 16-bit units. If
write/read operation is changed in progress, normal
operation will not be performed.
(2) Timer Y can select either writing data to both the latch and
the timer at the same time or writing data only by the timer
Y write control bit (b0) in the timer Y control register
(address 0039
16
). When writing to the latch only, if a value
is written to the timer Y address, the value is set into the
reload latch and the timer is updated at the next underflow.
After a reset release, if a value is written to the timer Y
address, the value is set into the timer and the timer latch at
the same time, because they are written simultaneously.
When writing to the latch only, if the write timing to the
high-order reload latch and the underflow timing are almost
the same, the value is set into the timer and the timer latch at
the same time. At this time, count is stopped during write
operation to the high-order reload latch.
(3) Switch the frequency division or count source* while the
timer count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-
chip oscillator mode, X
IN
mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
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