
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 100 of 134
38D5 Group
NOTES:
1. Relationship between system clock
φ
frequency and power source voltage is shown in the graph below.
2. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.
3. 12.5 MHz
<
f(X
IN
)
≤
16 MHz is not available in the frequency/2 mode.
4. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and
operatin temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency
oscillator.
5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(X
CIN
) < f(X
IN
)/3.
<System clock
φ
frequency>
<Main clock X
IN
frequency>
Table 26
Recommended operating conditions (4)
(V
CC
= 1.8 to 5.5 V, V
SS
= 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Typ.
Unit
Min.
Max.
6.25
f(CNTR
0
)
f(CNTR
1
)
Timer X and Timer Y
Input frequency (duty cycle 50%)
4.5
≤
V
CC
≤
5.5V
4.0
≤
V
CC
<
4.5V
2.0
≤
V
CC
<
4.0V
V
CC
<
2.0V
4.5
≤
V
CC
≤
5.5V
4.0
≤
V
CC
<
4.5V
2.0
≤
V
CC
<
4.0V
V
CC
<
2.0V
4.5
≤
V
CC
≤
5.5V
4.0
≤
V
CC
<
4.5V
2.0
≤
V
CC
<
4.0V
V
CC
<
2.0V
4.5
≤
V
CC
≤
5.5V
2.0
≤
V
CC
<
4.5V
V
CC
<
2.0V
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
2
×
Vcc
4
Vcc
5
×
Vcc
8
16
4
×
Vcc
8
2
×
Vcc
10
×
Vcc
16
6.25
4
Vcc
5
×
Vcc
8
16
8.0
20
×
Vcc
32
80
f(Tclk)
Timer X, Timer Y,
Timer 1, Timer 2,
Timer 3, Timer 4 clock input frequency
(Count source frequency of each timer)
f(
φ
)
System clock
φ
frequency
(1)
f(X
IN
)
Main clock input frequency
(duty cycle 50%)
(2)(3)
1.0
1.0
1.0
f(X
CIN
)
Sub-clock oscillation frequency
(duty cycle 50%)
(4)(5)
32.768
S
φ
[MHz]
6.25
4.0
2.0
1.0
0
1.8 2.0
4.0
4.5
5.5 [V]
Power source voltage
M
I
[MHz]
16
8.0
4.0
1.0
0
1.8 2.0
4.5
5.5 [V]
Power source voltage
QzROM VERSION