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| 型號(hào)： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 63/141頁(yè) |
| 文件大?。?/td> | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 63 of 134
38D5 Group
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock
φ
stops at an
“H” level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values * to
generate the wait time required for oscillation stabilization to
timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and
high-order 8 bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count
source, and the output of timer 1 is forcibly connected to timer 2. In
this time, bits 0 to 5 of the timer 12 mode register are cleared to “0”.
The values of the timer 12 frequency divider selection register
are not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to be
disabled (“0”) before executing the STP instruction.
*:
Reference (Set values according to your oscillator and system.)
OSCSEL = “L” of the QzROM version and flash memory
version:
..........................................................................0005
16
or more
OSCSEL = “H” of the QzROM version:
..........................................................................01FF
16
or more
When an external interrupt is received, the clock set according to
the OSCSEL pin state starts oscillating in the QzROM version.
The operation mode at returning is decided by the clock that set
according to the OSCSEL pin state.
Bits 3, 5, 6, and 7 of CPUM and bit 0 of CPUM2 are forcibly
changed by the OSCSEL pin state. In the flash memory version,
the on-chip oscillator starts oscillating and the operation mode at
returning is set to on-chip oscillator mode. The bit 3 of CPUM is
changed to “0”, bits 5, 6 and 7 of CPUM are changed to “1”, and
the bit 0 of CPUM2 is changed to “0” forcibly.
Oscillator restarts when reset occurs or an interrupt request is
received, but the system clock
φ
is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit
oscillation to stabilize.
(2) Wait Mode
If the WIT instruction is executed, only the system clock
φ
stops
at an “H” state. The states of main clock, on-chip oscillator and
sub clock are the same as the state before executing the WIT
instruction, and oscillation does not stop. Since supply of system
clock
φ
is started immediately after the interrupt is received, the
instruction can be executed immediately.
Fig. 60 Ceramic resonator circuit example
Fig. 61 External clock input circuit
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf
Rd
Note
: Insert a damping resistor if required.
The resistance will vary depending on the oscillator and the oscillation drive
capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer's data sheet specifies that a feedback
resistor be added external to the chip though a feedback resistor exists on-chip,
insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Rd
X
CIN
X
COUT
X
IN
X
OUT
External oscillation circuit
C
COUT
Open
V
CC
V
SS
C
CIN
Rf
Rd
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