參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 47/141頁
文件大小： 2027K
代理商： 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 47 of 134
38D5 Group
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For serial I/O2, the transmitter and the receiver must use the
same clock.
When the internal clock is selected as the operating clock, a write
signal to the serial I/O2 register initializes serial I/O2 and
transmission/reception starts.
When the external clock is selected as the operating clock, a
write signal to the serial I/O2 register initializes the serial I/O2
counter and transmission/reception is enabled. Inputting the
external clock starts transmission/reception. To write to the serial
I/O2 register when the external clock is selected as the operating
clock, perform writing while SCLK2 is set to “H”.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8bits which control
various serial I/O functions.
Fig. 38 Structure of serial I/O2 control registers
Fig. 39 Block diagram of serial I/O2
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 :
φ
SOURCE/8
0 0 1 :
φ
SOURCE/16
0 1 0 :
φ
SOURCE/32
0 1 1 :
φ
SOURCE/64
1 0 0 : Not available
1 0 1 : Not available
1 1 0 :
φ
SOURCE/128
1 1 1 :
φ
SOURCE/256
Serial I/O2 port selection bit
0 : I/O port
1 : S
OUT2
, S
CLK2
signal pin
P4
5
/S
OUT2
P-channel output disable bit
0 : CMOS output (at output mode)
1 : N-channel open-drain output (at output mode)
Transfer direction selection bit
0 : LSB first
1 : MSB first
Serial I/O2 synchronous clock selection bit
0 : External clock
1 : Internal clock
S
RDY2
output selection bit
0 : I/O port P4
7
1 : S
RDY2
signal output
b7
Serial I/O2 control register
(SIO2CON: address 001D
16
)
b0
Note1:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)
P4
7
/S
RDY2
φ
SOURCE
Notes:
1: It is selected by the serial I/O2 synchronous clock selection bit, S
RDY2
output
selection bit and serial I/O2 port selection bit.
2:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
Frequency
divider
1/8
1/16
1/32
1/64
1/128
1/256
Synchronous circuit
S
C
P4
6
/S
CLK2
P4
5
/S
OUT2
P4
4
/S
IN2
Serial I/O2 counter (3)
Serial I/O2 register (8)
P4
7
latch
P4
6
latch
“0”
P4
5
latch
“0”
Serial I/O2 synchronous
clock selection bit “1”
“0”
External clock
(1)
“1”
Data bus
Serial I/O2
interrupt request
Internal
synchronous clock
selection bits
Serial I/O2 po“1”
(1)
Address 001F
16
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