參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 135/141頁
文件大小： 2027K
代理商： 38D5
(1/6)
REVISION HISTORY
38D5 Group Data Sheet
Rev.
Date
Description
Page
Summary
1.00
Aug 12, 2005
First edition issued
Pin name revised: CNVss
→
OSCSEL
Frequency name revised: ROSC
→
OCO
Mode name revised: Middle-, High-speed mode
→
Frequency/2, 4, 8 mode
2.00
Jan 23, 2006
Bit names of some registers:
1. ROSC stop bit
→
On-chip oscillator stop bit
2. STP instruction disable bit
→
STP instruction function selection bit
3. Vector 1 enable bit (RC0)
→
ROM correction address 1 enable bit (RC0)
4. Vector 2 enable bit (RC1)
→
ROM correction address 2 enable bit (RC1)
5. Vector control bit (RC2)
→
ROM correction memory selection bit (RC2)
1
Description, Power source voltage and Power dissipation revised.
6
Table 2 Pin description (1): Some description of Port P1 Function revised.
7
Table 3 Pin description (2): Description of OSCSEL added.
Fig. 5 Memory expansion plan, Table 4 Support products
M38D59GFFP/HP, M38D59GCFP/HP added.
13
Some description revised.
Fig. 8 Structure of CPU mode register: Note on on-chip oscillator added.
Fig. 9 Switch procedure of CPU mode register: Initial values of CPUM2 added and
initial value of CPUM revised.
14
Fig. 10 Memory map diagram:
Reserved ROM area FFD4
16
to FFDC
16
→
FFD0
16
to FFDC
16
Note on ROM correction vector added.
15
Fig. 11 Memory map of special function register (SFR):
“Reserved area” is added to address 0FFD
16
, and Note added.
22
Table 8 Termination of unused pins: X
IN
and X
OUT
pin termination added.
52
ROM CORRECTION FUNCTION:
Description and some bit names revised and Fig. 47 Memory map of M38D58 added.
53
Initial Value of Watchdog Timer: Some description added.
Standard Operation of Watchdog Timer: Some description eliminated.
Bit 6 of Watchdog Timer Control Register added.
Note 2 revised.
Fig. 50 Structure of Watchdog timer control register:
Name of bit 6 and description of its function revised.
55
Fig. 55 Reset sequence revised.
57
Fig. 56 Internal state at reset: ROM correction address 1 (low-order), ROM
correction address 2 (high-order) and ROM correction address 2 (low-order)
revised.
58
Oscillation Control (1) Stop Mode: Some description revised.
59
Fig. 58 Clock generating circuit block diagram:
“or ROSC clock division ratio selection bit” eliminated.
60
Fig. 60 State transitions of system clock
on-chip oscillator mode: f(OCO)
→
f(OCO)/32,
Note 8 to Note 10 revised and Note 12 added.
61-65
QzROM programming mode (Overview, Pin description, Pin connection diagram,
Connection example) added.
68
(6) Wiring to OSCSEL pin revised.
69
QzROM Receive Flow added.
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