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參數(shù)資料
| 型號： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 27/141頁 |
| 文件大?。?/td> | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 27 of 134
38D5 Group
INTERRUPTS
The 38D5 Group interrupts are vector interrupts with a fixed
priority scheme, and generated by 16 sources among 17 sources:
6 external, 10 internal, and 1 software.
The interrupt sources, vector addresses
(1)
, and interrupt priority
are shown in Table 11.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 18 shows an interrupt control diagram.
An interrupt requests is accepted when all of the following
conditions are satisfied:
Interrupt disable flag ................................ “0”
Interrupt request bit .................................. “1”
Interrupt enable bit ................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
3. INT
0
, and INT
1
input pins are selected by the interrupt edge selection register (INTEDGE).
Table 11
Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses
(1)
High
FFFD
16
FFFB
16
Interrupt Request
Generating Conditions
Remarks
Low
FFFC
16
FFFA
16
Reset
(2)
INT
0
(INT
00
or
INT
01
)
(3)
INT
1
(INT
10
or
INT
11
)
(3)
INT
2
1
2
At reset
At detection of either rising or falling
edge of INT
0
input
Non-maskable
External interrupt (active edge selectable)
3
FFF9
16
FFF8
16
At detection of either rising or falling
edge of INT
1
input
External interrupt (active edge selectable)
4
FFF7
16
FFF6
16
At detection of either rising or falling
edge of INT
2
input
At falling of ports P2
0
P2
3,
P4
4
P4
7
input logical level AND
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At completion of serial I/O1 data receive Valid only when serial I/O1 is selected
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data
transmit/receive
At detection of either rising or falling
edge of CNTR
0
input
At timer Y underflow
At detection of either rising or falling
edge of CNTR
1
input
At completion of A/D conversion
At BRK instruction execution
Valid when INT
2
interrupt is selected
External interrupt (active edge selectable)
Valid when Key input interrupt is
selected
External interrupt (falling valid)
Key input
(key-on wakeup)
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
Serial I/O1 receive
Serial I/O1 transmit
5
FFF5
16
FFF4
16
6
7
8
9
10
11
12
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
Valid only when serial I/O1 is selected
Serial I/O2
13
FFE5
16
FFE4
16
CNTR
0
14
FFE3
16
FFE2
16
External interrupt (active edge selectable)
Timer Y
CNTR
1
15
FFE1
16
FFE0
16
External interrupt (active edge selectable)
A/D conversion
BRK instruction
16
17
FFDF
16
FFDD
16
FFDE
16
FFDC
16
Non-maskable software interrupt
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