參數(shù)資料
型號： 38D5
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 106/141頁
文件大?。?/td> 2027K
代理商： 38D5
Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 106 of 134
38D5 Group
NOTE:
1. The P4
1
/TxD P-channel output disable bit (bit 4 of address 001B
16
) of UART control register is “0”.
NOTE:
1. The P4
1
/TxD P-channel output disable bit (bit 4 of address 001B
16
) of UART control register is “0”.
Fig 95. Circuit for measuring output switching characteristics
Table 33
Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
Symbol
Parameter
Limits
Typ
Unit
Min.
Max.
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
td(S
CLK1
-T
x
D)
tv(S
CLK1
-T
x
D)
tr(S
CLK1
)
tf(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
tf(S
CLK2
)
td(S
CLK2-
S
OUT2
)
tv(S
CLK2-
S
OUT2
)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
(1)
Serial I/O1 output valid time
(1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 clock output falling time
Serial I/O2 output delay time
Serial I/O2 output valid time
tc(S
CLK1
)/2-30
tc(S
CLK1
)/2-30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140
30
30
30
tc(S
CLK2
)/2-30
tc(S
CLK2
)/2-30
40
140
30
Table 34
Switching characteristics (2)
(V
CC
= 1.8 to 4.0 V, V
SS
= 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
Symbol
Parameter
Limits
Typ
Unit
Min.
Max.
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
td(S
CLK1
-T
x
D)
tv(S
CLK1
-T
x
D)
tr(S
CLK1
)
tf(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
tf(S
CLK2
)
td(S
CLK2-
S
OUT2
)
tv(S
CLK2-
S
OUT2
)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
(1)
Serial I/O1 output valid time
(1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 clock output falling time
Serial I/O2 output delay time
Serial I/O2 output valid time
tc(S
CLK1
)/2-80
tc(S
CLK1
)/2-80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
350
-30
80
80
tc(S
CLK2
)/2-80
tc(S
CLK2
)/2-80
80
350
-30
Measurement output pin
100pF
CMOS output
Measurement output pin
100pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B
16
) is “1.”
(N-channel open-drain output mode)
1k
QzROM VERSION
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