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參數(shù)資料
| 型號： | 38D5 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 43/141頁 |
| 文件大?。?/td> | 2027K |
| 代理商： | 38D5 |
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Rev.3.01
REJ03B0158-0301
Aug 08, 2007
Page 43 of 134
38D5 Group
SERIAL INTERFACE
SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O mode selection bit of the serial I/O1 control register
to “1”.
For clock synchronous serial I/O1, the transmitter and the
receiver must use the same clock. If an internal clock is used,
transfer is started by a write signal to the TB/RB.
Fig. 33 Block diagram of clock synchronous serial I/O1
Fig. 34 Operation of clock synchronous serial I/O1 function
1/4
1/4
F/F
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Data bus
Transmit shift register
Serial I/O1 control register
Address 0018
16
Address 0018
16
Address 0019
16
Address 001A
16
P4
0
/R
X
D
P4
2
/S
CLK1
P4
3
/S
RDY1
P4
1
/T
X
D
φ
SOURCE
Note1:
φ
SOURCE indicates the followings:
X
IN
input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register
Overrun error (OE)
detection
Notes 1
: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or
after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2
: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3
: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal S
RDY
D
7
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