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參數(shù)資料
| 型號： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁數(shù)： | 9/98頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
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R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
9
63
2
PCS /
1
CTS /
ENRX /PIO19 Input/Output
Clear to send/Enable Receiver Request signal for
asynchronous serial port 1. when
AUXCON register is cleared and the FC bit in the serial port
1 control register is set the
ENRX signal is enabled. Other
when
1
ENRX bit is set and the FC bit is set the
1
ENRX signal is enabled.
Bus Interface
Bus high enable/address enable. During a memory access, the
BHE and (AD0 or A0) encodings indicate what type of the
bus cycle. BHE is asserted during T1 and keeps the asserted
to T3 and Tw. This pin is floating during bus hold and reset.
BHE and (AD0 or A0) Encodings
BHE AD0 or A0
0
0
1
1
1
Refresh
The address portion of the AD bus can be enabled or disabled
by DA bit in the LMCS and UMCS register during LCS or
UCS bus cycle access, if BHE /ADEN is held high during
power-on reset. The BHE /ADEN with a internal weak
pull-up register, so no external pull-up register is required.
The AD bus always drives both address and data during LCS
or UCS bus cycle access, if the BHE /ADEN pin with
external pull-low resister during reset.
Write strobe. This pin indicates that the data on the bus is to
be written into a memory or an I/O device. WR is active
during T2, T3 and Tw of any write cycle, floats during a bus
hold or reset.
Read Strobe. Active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.
RD floats during bus hold or reset.
Address latch enable. Active high. This pin indicates that an
address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during
ONCE mode and is never floating during a bus hold or reset.
Asynchronous ready. This pin performs the microcontroller
that the address memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that is
asynchronous to CLKOUTA and is active high. The falling
edge of ARDY must be synchronized to CLKOUTA. Tie
ARDY high, the microcontroller is always asserted in the
ready condition. If the ARDY is not used, tie this pin low to
yield control to SRDY.
Bus cycle status. These pins are encoded to indicate the bus
status.
2
S can be used as memory or I/O indicator. S can
be used as DT/R indicator. These pins are floating during
hold and reset.
Bus Cycle Encoding Description
2
S
1
S
0
S
0
ENRX bit in the
1
Type of Bus Cycle
0
1
0
Word transfer
High byte transfer (D15-D8)
Low byte transfer (D7-D0)
4
BHE /ADEN
Output/Input
5
WR
Output
6
RD
Output
7
ALE
Output
8
ARDY
Input
9
10
11
2
1
0
S
S
S
Output
Bus Cycle
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R8821 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8822 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER |
| R8822I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
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