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參數(shù)資料
| 型號(hào)： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁(yè)數(shù)： | 62/98頁(yè) |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
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R DC
15. Timer Control Unit
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
62
There are three 16-bit programmable timers in the R8820LV. The timer operation is independent of the CPU. The three timers
can be programmed as a timer element or as a counter element. Timers 0 and 1 are each connect to two external pins (TMRIN0,
TMROUT0, TMRIN1, TMROUT1) which can be used to count or time external events, or they can be used to generate a
variable-duty-cycle waveforms. Timer 2 is not connected any external pins. It can be used as a prescale to timer 0 and timer 1
or as a DMA request source.
These bits definition for timer 0 are same as the bits of register 5Eh for timer 1.
Offset : 50h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Timer 0 Count Register
TC15 - TC0
Counter
Element
&
Control
Logic
Microprocessor Clock
50h,Timer 0 Count Register
58h,Timer 1 Compare Register
52h,54h,Timer0 Maxcount Compare Register
5Ah,5Ch,Timer 1 Maxcount Compare Register
62h,Timer 2 Count Register
60h,Timer 2 count Register
Interrupt Request
5Eh,Timer 1 Control Register
56h,Timer 0 Control Register
Internal Address/Data Bus
TMROUT1
TMROUT2
16 bit
16 bit
Timer / Counter Unit Block
16 bit
DMA Request
66h,Timer 2 Control Register
TMRIN1 TMRIN0
(Timer2)
(Timer0,1,2)
Offset : 56h
Reset Value : 0000h
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Timer 0 Mode / Control Register
CONT
ALT
EXT
P
RTG
MC
0
0
0
0
0
RIU
INT
EN
0
INH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R8821 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8822 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER |
| R8822I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
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