參數(shù)資料
型號(hào)： R8820LV
廠商： Electronic Theatre Controls, Inc.
英文描述： 16-BIT RISC MICROCONTROLLER
中文描述： 16位RISC微控制器
文件頁數(shù)： 57/98頁
文件大?。?/td> 1000K
代理商： R8820LV
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
57
Bit 15:
DM
/
IO, Destination Address Space Select.
Set 1: The destination address is in memory space.
Set 0: The destination address is in I/O space.
Bit 14: DDEC
, Destination Decrement.
Set 1: The destination address is automatically decrement after each transfer.
The
B
/W (bit 0) bit determines the decrement value which is by 1 or 2 When both DDEC and DINC bits are
set to 1, the address remains constant
Set 0 : Disable the decrement function.
Bit 13: DINC
, Destination Increment.
Set 1: The destination address is automatically increment after each transfer.
The
B
/W (bit 0) bit determines the increment value which is by 1 or 2
Set 0 : Disable the decrement function.
Bit 12: SM/
IO, Source Address Space Select.
Set 1: The Source address is in memory space.
Set 0: The Source address is in I/O space
Bit 11: SDEC
, Source Decrement.
Set 1: The Source address is automatically decrement after each transfer.
The
B
/W (bit 0) bit determines the decrement value which is by 1 or 2 When both SDEC and SINC bits are set
to 1, the address remains constant
Set 0 : Disable the decrement function.
Bit 10: SINC
, Source Increment.
Set 1: The Source address is automatically increment after each transfer.
The
B
/W (bit 0) bit determines the increment value which is by 1 or 2
Set 0 : Disable the decrement function
Bit 9 : TC
, Terminal Count.
Set 1: The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0.
Set 0: The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0.
Unsynchronized DMA transfer is always terminated when the DMA transfer count register reaches 0,
regardless the setting of this bit.
Bit 8 : INT
, Interrupt.
Set 1: DMA unit generates an interrupt request when complete the transfer count .
The TC bit must set to 1 to generate an interrupt.
Bit 7-6: SYN1-SYN0
, Synchronization Type Selection.
SYN1
,
SYN0
--
Synchronization Type
0 , 0 -- Unsynchronized
0 , 1 -- Source synchronized
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