參數(shù)資料
型號： R8820LV
廠商： Electronic Theatre Controls, Inc.
英文描述： 16-BIT RISC MICROCONTROLLER
中文描述： 16位RISC微控制器
文件頁數(shù)： 44/98頁
文件大小： 1000K
代理商： R8820LV
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
44
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of the register 44h
(Slave Mode) , This register is for timer 2 interrupt control,
reset value is 0000h
Bit 15- 4 :
Reserved
Bit 3 : MSK
, Mask.
Set 1: Mask the interrupt source of the Timer 2
Set 0: Enable the Timer 2 interrupt.
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of the register 44h
(Master Mode)
Bit 15-8 :
Reserved
Bit 7: ETM
, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.
The low go high edge will be latched (one level) till this interrupt is been serviced.
Bit 6:
SFNM, Special Fully Nested Mode.
Set 1: Enable the special fully nested mode of INT0.
Bit 5: C,
Cascade Mode. Set this bit to 1 to enable the cascade mode for INT1 or INT0.
Bit 4: LTM
, Level-Triggered Mode.
Set 1: Interrupt is triggered by high active level
Set 0 : Interrupt is triggered by low go high edge.
Bit 3 : MSK
, Mask.
Set 1: Mask the interrupt source of the INT0
Set 0: Enable the INT0 interrupt.
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of the register 44h
(Slave Mode),For Timer 1 interrupt control register,
reset value is 0000h
Bit 15-4
: Reserved
Bit 3: MSK
, Mask.
Set 1: Mask the interrupt source of the timer 1
INT0 Control Register
Offset : 38h
Reset Value : 000Fh
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
MSK
PR2
PR1
PR0
LTM
C
SFNM
ETM
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