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參數(shù)資料
| 型號(hào)： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁數(shù)： | 31/98頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
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R DC
12. Chip Select Unit
The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device.
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
31
The chip selects are programmed through five peripheral control registers (A0h, A2h, A4h, A6h, A8h). And all of the
chip selects can be insert wait states by programmed the peripheral control register.
12.1
UCS
TheUCSdefault to active on reset for program code access. The memory active range is upper 512k (80000h – FFFFFh),
which is programmable. And the default memory active range ofUCS is 64k ( F0000h – FFFFFh).
TheUCS active to drive low four CLKOUTA oscillators if no wait state inserts. There are three wait-states insert toUCS
active cycle on reset.
Bit 15
: Reserved
Bit 14-12 : LB2-LB0
, Memory block size selection forUCS chip select pin.
TheUCS chip select pin active region can be configured by the LB2-LB0.
The default memory block size is from F0000h to FFFFFh.
LB2, LB1, LB0
----
Memory Block size
,
Start address
,
End Address
1 , 1 , 1 ---- 64k , F0000h , FFFFFh
1 , 1 , 0 ---- 128k , E0000h , FFFFFh
1 , 0 , 0 ---- 256k , C0000h , FFFFFh
0 , 0 , 0 ---- 512k , 80000h , FFFFFh
Bit 11-8
: Reserved
Bit 7 : DA
, Disable Address. If the
BHE
/ADEN pin is held high on the rising edge of RST , then the DA bit is valid to
enable/disable the address phase of the AD bus. If the
BHE
/ADEN pin is held high on the rising edge of RST , the
AD bus always drive the address and data.
Set 1 : Disable the address phase of the AD15 – AD0 bus cycle whenUCSis asserted.
Set 0 : Enable the address phase of the AD15 – AD0 bus cycle whenUCSis asserted.
Bit 6-3
: Reserved
Bit 2 : R2
, Ready Mode. This bit is used to configure the ready mode forUCSchip select.
Set 1: external ready is ignored.
Set 0: external ready is required.
Bit 1-0 : R1-R0
, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to theUCSmemory area.
Upper Memory Chip Select Register
Offset : A0h
Reset Value :F03Bh
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
1
LB2 - LB0
0
0
0
0
DA
0
1
1
1
R2
R1
R0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| R8821 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8822 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER |
| R8822I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
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