
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
39
INTO Detected Over Flow Exception 04h
Array Bounds Exception
Undefined Opcode Exception
ESC Opcode Exception
Timer 0
Reserved
DMA 0/INT5
DMA 1/INT6
INT0
INT1
INT2
INT3
INT4
Asynchronous Serial port 1
Timer 1
Timer 2
Asynchronous Serial port 0
Reserved
Note * : When the interrupt occurs in the same time, the priority is (1-1 > 1-2) ; (2-1> 2-2 > 2-3)
10h
14h
18h
1Ch
20h
1
1
1
1
2-1
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h-1Fh
08
*/**
**
**
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
0A
0B
0C
0D
0E
0F
10
11
08
08
14
3
4
5
6
7
8
9
9
2-2
2-3
9
*/**
*/**
Note **: The interrupt types of these sources are programmable in slave mode.
13.3 Interrupt Request
When an interrupt is request, the internal interrupt controller verifies the interrupt is enable (The IF flag is enable, no MSK bit
set ) and that there are no higher priority interrupt requests being serviced or pending. If the interrupt is granted , the interrupt
controller uses the interrupt type to access a vector from the interrupt vector table.
If the external INT is active (level-trigger) to request the interrupt controller service, and the INT pins must hold till the
microcontroller enter the interrupt service routine. There is no interrupt-acknowledge output when running in fully nested
mode, so it should use PIO pin to simulate the interrupt-acknowledge pin if necessary.
13.4 Interrupt Acknowledge
The processor requires the interrupt type as an index into the interrupt table. The internal interrupt can provide the interrupt
type or an external controller can provide the interrupt type.
The internal interrupt controller provides the interrupt type to processor without external bus cycles generation. When an
external interrupt controller is supplying the interrupt type, the processor generates two acknowledge bus cycles, and the
interrupt type is written to the AD7-AD0 lines by the external interrupt controller.