
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
73
Long Break : The TXD is driven low for grater than (2M+3) bit times;
Short break : The TXD is driven low for grater than M bit times;
* M= start bit + data bits number + parity bit + stop bit
Bit 10 : TB8
, Transmit Bit 8. This bit is transmitted as ninth data bit in mode 2 and mode 3. This bit is cleared after every
transmission.
Bit 9: FC
, Flow Control Enable.
Set 1: Enable the hardware flow control for serial port 0.
Set 0 : Disable the hardware flow control for serial port 0.
Bit 8 : TXIE
, Transmitter Ready Interrupt Enable. When the Transmit Holding Register is empty ( THRE bit in Status
Register is set ),it will have an interrupt occurs.
Set 1: Enable the Interrupt.
Set 0 : Disable the interrupt.
Bit 7: RXIE,
Receive Data Ready Interrupt Enable. When the receiver buffer contains valid data ( RDR bit in Status
Register is set) , it will generate an interrupt.
Set 1: Enable the Interrupt.
Set 0 : Disable the interrupt.
Bit 6 : TMODE
, Transmit Mode.
Set 1: Enable the TX machines.
Set 1: Disable the TX machines.
Bit 5: RMODE
, Received Mode.
Set 1: Enable the RX machines.
Set 1: Disable the RX machines.
Bit 4: EVN,
Even Parity. This bit is valid only when the PE bit is set.
Set 1: the even parity checking is enforced (even number of 1s in frame).
Set 0: odd parity checking is enforced (odd number of 1s in frame).
Bit 3: PE
, Parity Enable.
Set 1 : Enable the parity checking.
Set 0 : Disable the parity checking.
Bit 2-0: MODE
, Mode of Operation.
( bit 2, bit 1, bit 0) MODE
( 0 , 0 , 1)
( 0 , 1 , 0)
( 0 , 1 , 1)
( 1 , 0 , 0)
Data Bits
Parity Bits
1 or 0
N/A
1 or 0
N/A
Stop Bits
Mode 1
Mode 2
Mode 3
Mode 4
7 or 8
9
8 or 9
7
1
1
1
1