
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
35
The base address memory block can be located anywhere within the 1M bytes memory space, exclusive of the areas associated
with theMCS4, LCSand MCSchip elects. If the chip selects are mapped to I/O space, the access range is 64k bytes.
PCS6 –PCS5 can be configured from 0 wait-state to 3 wait-states.
PCS3 – PCS0 can be configured from 0 wait-state to 15
wait-states.
Bit 15-7 : BA19-BA11
, Base Address. BA19-BA11 correspond to bit 19-11 of the 1M bytes (20-bits) programmable base
address of thePCS chip select block.
When thePCS chip selects are mapped to I/O space, BA19-BA16 must be wrote to 0000b because the I/O address
bus in only 64K bytes (16-bits) wide.
PCSx address range:
PCS0 : Base Address - Base Address+255
PCS1 : Base Address+256 - Base Address+511
PCS2 : Base Address+512 - Base Address+767
PCS3 : Base Address+768 - Base Address+1023
PCS4 : Base Address+1280 - Base Address+1535
PCS5 : Base Address+1536 - Base Address+1791
Bit 6-4
: Reserved
Bit 3: R3
;
Bit 1-0: R1,R0
,Wait-State Value. The R3,R1,R0 determines the number of wait-states inserted into a PCS3 -
PCS0 access.
R3, R1, R0 -- Wait States
0, 0, 0 -- 0
0, 0, 1 -- 1
0, 1, 0 -- 2
0, 1, 1 -- 3
1, 0, 0 -- 5
1, 0, 1 -- 7
1, 1, 0 -- 9
1, 1, 1 -- 15
Bit 2
:
R2
, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS3 -PCS0 chip selects.
The R3,R1,R0 bits determine the number of wait state to insert.
set to 1: external ready is ignored
Peripheral Chip Select Register
Offset : A4h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
BA19 - BA11
1
1
1
R3
R2
R1
R0