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參數(shù)資料
| 型號： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁數(shù)： | 47/98頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
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R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
47
(Master Mode),
Reset value undefine
Bit 15 : DHLT
, DMA Halt.
Set 1: halts any DMA activity. When non-maskable interrupts occur.
Set 0: When an IRET instruction is executed.
Bit 14-3 :
Reserved.
Bit 2-0 : TMR2-TMR0
,
Set 1: indicates the corresponding timer has an interrupt request pending.
(Slave Mode),
Reset value is 0000h
Bit 15 : DHLT
, DMA Halt.
Set 1: halts any DMA activity. When non-maskable interrupts occur.
Set 0: When an IRET instruction is executed.
Bit 14-3 :
Reserved.
Bit 2-0 : TMR2-TMR0
,
Set 1: indicates the corresponding timer has an interrupt request pending.
(Master Mode)
The Interrupt Request register is a read-only register. For internal interrupts (SP0, SP1, D1/I6, D0/I5, and TMR), the
corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt
acknowledge. For INT4-INT0 external interrupts, the corresponding bit (I4-I0) reflects the current value of the external signal.
Bit 15-11 :
Reserved.
Bit 10 :
SP0
, Serial Port 0 Interrupt Request. Indicates the interrupt state of the serial port 0.
Bit 9 : SP1
, Serial Port 1 Interrupt Request. Indicates the interrupt state of the serial port 1.
Bit 8-4 : I4-I0
, Interrupt Requests.
Set 1: The corresponding INT pin has an interrupt pending.
Bit 3-2 : D1/I6-D0/I5
, DMA Channel or INT Interrupt Request.
Interrupt Status Register
Offset : 30h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
TMR2 TMR1 TMR0
DHLT
Interrupt Request Register
Offset : 2Eh
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
D0/I5
Res
TMR
D1/I6
I0
I1
I2
I3
I4
SP1
SP0
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| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
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