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參數(shù)資料
| 型號： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁數(shù)： | 42/98頁 |
| 文件大小： | 1000K |
| 代理商： | R8820LV |
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R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
42
(Master Mode)
Bit 15- 8, bit 6-5 :
Reserved
Bit 7: ETM
, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.
The low go high edge will be latched (one level) till this interrupt is been serviced.
Bit 4: LTM
, Level-Triggered Mode.
Set 1: Interrupt is triggered by high active level
Set 0 : Interrupt is triggered by low go high edge.
Bit 3 : MSK
, Mask.
Set 1: Mask the interrupt source of the INT4
Set 0: Enable the INT4 interrupt.
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of 44h
(Master Mode)
Bit 15- 8, bit 6- 5 :
Reserved
Bit 7: ETM
, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.
The low go high edge will be latched (one level) till this interrupt is been serviced.
Bit 4: LTM
, Level-Triggered Mode.
Set 1: Interrupt is triggered by high active level
Set 0 : Interrupt is triggered by low go high edge.
Bit 3 : MSK
, Mask.
Set 1: Mask the interrupt source of the INT3
Set 0: Enable the INT3 interrupt.
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of 44h
INT4 Control Register
Offset : 40h
Reset Value : 000Fh
2
3
0
5
6
8
9
11
12
14
15
MSK
PR2
PR0
LTM
INT3 Control Register
Offset : 3Eh
Reset Value : 000Fh
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
MSK
PR2
PR1
PR0
LTM
ETM
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