
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
63
Bit 15 – 0: TC15-TC0
, Timer 0 Count Value. This register contains the current count of timer 0. The count is incremented by
one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is
configured the external clock select bit to refer the TMRIN1 signal.
Bit 15-0 : TC15 – TC0
, Timer 0 Compare A Value.
Bit 15-0 : TC15 – TC0
, Timer 0 Compare B Value.
Bit 15: EN
, Enable Bit.
Set 1: The timer 1 is enable.
Set 0: The timer 1 is inhibited from counting.
TheINH bit must be set 1 during writing the EN bit, and theINH bit and EN bit must be in the same write.
Bit 14:
INH , Inhibit Bit. This bit is allows selective updating the EN bit. TheINH bit must be set 1 during writing the EN
bit, and both theINH bit and EN bit must be in the same write. This bit is not stored and is always read as 0.
Bit 13: INT
, Interrupt Bit.
Set 1: A interrupt request is generated when the count register equals a maximum count. If the timer is configured in
dual max-count mode, an interrupt is generated each time the count reaches max-count A or max-count B
Set 0: Timer 1 will not issue interrupt request.
Bit 12: RIU
, Register in Use Bit.
Set 1: The Maxcount Compare B register of timer 1 is being used
Offset : 52h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Timer 0 Maxcount Compare A Register
TC15 - TC0
Offset : 54h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Timer 0 Maxcount Compare B Register
TC15 - TC0
Offset : 5Eh
Reset Value : 0000h
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Timer 1 Mode / Control Register
CONT
ALT
EXT
P
RTG
MC
0
0
0
0
0
RIU
INT
EN
0
INH