
R DC
16. Watchdog Timer
R8820LV has one independent watchdog timer, which is programmable.
The watchdog timer is active after reset
and the
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
68
timeout count with a maximum count value. The keyed sequence ( 3333h, CCCCh ) must be written to the register (E6h) first
then writing new configuration to the Watchdog Timer Control Register. It is a single write so every one writing to Watchdog
Timer Control Register must follow the rule.
To read the Watchdog Timer Control Register, the keyed sequence (5555h, AAAAh) must be written to the register (E6h) first.
The current count should be reset before modifying the Watchdog Timer timeout period to ensure that an immediate timeout
dose not occur.
Bit 15: ENA
, Enable Watchdog Timer.
Set 1 : Enable Watchdog Timer.
Set 0 : Disable Watchdog Timer.
Bit 14: WRST
, Watchdog Reset.
Set 1: WDT generates a system reset when WDT timeout count is reached.
Set 0 : WDT generates a NMI interrupt when WDT timeout count is reached if the NMIFLAG bit is 0. If the NMIFLAG
bit is 1, the WDT will generate a system reset when timeout.
Bit 13: RSTFLAG
, Reset Flag. When watchdog timer reset event has occurred, hardware will set this bit to 1. This bit will be
cleared by any keyed sequence write to this register or external reset. This bit is 0 after an external reset or 1 after
watchdog timer reset.
Bit 12: NMIFLAG
, NMI Flag. After WDT generates a NMI interrupt, this bit will be set to 1 by H/W. This bit will be cleared
by any keyed sequence write to this register.
Bit 11-8 : Reserved.
Bit 7-0 : COUNT
, Timeout Count. The COUNT setting determines the duration of the watchdog timer timeout interval.
Exponent
2
b. The Exponent of the COUNT setting:
a. The duration equation :
Duration =
/ Frequency
(Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, Bit 0) = ( Exponent)
( 0 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = (N/A)
( x , x , x , x, x , x , x , x ) = ( 10 )
(x , x , x , x, x , x , 1 , 0 ) = ( 20 )
(x , x , x , x, x , 1 , 0 , 0 ) = ( 21 )
Watchdog Timer Control Register
Offset : E6h
Reset Value : C080h
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
N
R
W
ENA
COUNT
Res