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參數(shù)資料
| 型號： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁數(shù)： | 32/98頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
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R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
32
(R1,R0) = (0,0) -- 0 wait-state ; (R1,R0) = (0,1) -- 1 wait-state
(R1,R0) = (1,0) -- 2 wait-state ; (R1,R0) = (1,1) -- 3 wait-state
12.2
LCS
The lower 512k bytes (00000h-7FFFFh) memory region chip selects. The memory active range is programmable, which
has no default size on reset. So the A2h register must be programmed first before to access the target memory range. TheLCS
pin is not active on reset, but any read or write access to the A2h register activates this pin.
Bit 15
: Reserved
Bit 14-12
: UB2-UB0, Memory block size selection for LCSchip select pin
TheLCSchip select pin active region can be configured by the UB2-UB0.
TheLCSpin is not active on reset, but any read or write access to the A2h (LMCS) register activates this pin.
UB2, UB1, UB0
----
Memory Block size
,
Start address
,
End Address
0 , 0 , 0 ---- 64k , 00000h , 0FFFFh
0 , 0 , 1 ---- 128k , 00000h , 1FFFFh
0 , 1 , 1 ---- 256k , 00000h , 3FFFFh
1 , 1 , 1 ---- 512k , 00000h , 7FFFFh
Bit 11-8
: Reserved
Bit 7 : DA
, Disable Address. If the
BHE
/ADEN pin is held high on the rising edge of RST , then the DA bit is valid to
enable/disable the address phase of the AD bus. If the
BHE
/ADEN pin is held low on the rising edge of RST , the
AD bus always drive the address and data.
Set 1 : Disable the address phase of the AD15 – AD0 bus cycle whenLCSis asserted.
Set 0 : Enable the address phase of the AD15 – AD0 bus cycle whenLCSis asserted.
Bit 6 :
PSE
, PSRAM Mode Enable. This bit is used to enable PSRAM support for theLCSchip select memory space. The
refresh control unit registers E0h,E2h,E4h must be configured for auto refresh before PSRAM support is enabled.
PSE set to 1: PSRAM support is enable
PSE set to 0: PSRAM support is disable
Bit 5-3
: Reserved
Bit 2 : R2
, Ready Mode. This bit is used to configure the ready mode forLCSchip select.
Set 1: external ready is ignored.
Low Memory Chip Select Register
Offset : A2h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
0
UB2 - UB0
1
1
1
1
DA
PSE
1
1
1
R2
R1
R0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| R8821 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8822 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER |
| R8822I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
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