- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378123 > R8820LV (Electronic Theatre Controls, Inc.) 16-BIT RISC MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁(yè)數(shù)： | 60/98頁(yè) |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
60
The Destination-Synchronized Transfer figure shows the typical destination-synchronized transfer which differs from a source-
synchronized transfer in that two idle states are added to the end of the deposit cycle. The two idle states extend the DMA
cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the cycle. If the two idle states were
not inserted, the destination device would not have time to deassert its DRQ signal.
CLKOUTA
DRQ(Case1)
DRQ(Case2)
Fetch Cycle
Fetch Cycle
Source-Synchronized Transfers
T1
T2
T3
T4
T1
T2
T3
T4
NOTES:
Case1 : Current source synchronized transfer will not be immediately
followed by another DMA transfer.
Case2 : Current source synchronized transfer will be immediately
followed by antoher DMA transfer.
CLKOUTA
DRQ(Case1)
DRQ(Case2)
Fetch Cycle
Fetch Cycle
Destination-Synchronized Transfers
T1
T2
T3
T4
T1
T2
T3
T4
TI
TI
NETES:
Case1 : Current destination synchronized transfer will not be immediately
followed by another DMA transfer.
Case2 : Current destination synchronized transfer will be immediately
followed by another DMA transfer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RA258 | Silicon Rectifier Button-Cells |
| RA2505 | Silicon Rectifier Button-Cells |
| RB5P0010M | Video Interface ICs for TFT-LCDs |
| RB5P0020M | Video Interface ICs for TFT-LCDs |
| RB5P0050M | Video Interface ICs for TFT-LCDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R8821 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8822 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER |
| R8822I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。