參數(shù)資料
型號: R8820LV
廠商: Electronic Theatre Controls, Inc.
英文描述: 16-BIT RISC MICROCONTROLLER
中文描述: 16位RISC微控制器
文件頁數(shù): 54/98頁
文件大?。?/td> 1000K
代理商: R8820LV
R DC
14. DMA Unit
The DMA controller provides the data transfer between the memory and peripherals without the intervention of the CPU.
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
54
There are two DMA channels in the DMA unit. Each channel can accept DMA request from one of three sources:
external pin (DRQ0 for channel 0 or DRQ1 for channel 1) or serial port (port 0 or port 1) or Timer 2 overflow. The data
transfer from source to destination can be memory to memory ,or memory to I/O, or I/O to I/O, or I/O to memory. Either bytes
or words can be transferred to or from even or odd addresses and two bus cycles are necessary (read from source and write to
destination) for each data transfer.
14.1 DMA Operation
Every DMA transfer consists of two bus cycles (figure of Typical DMA Transfer) and the two bus cycles can not be separated
by a bus hold request, a refresh request or another DMA request. The registers ( CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h,
D6h, D4h, D2h, D0h) are used to configure and operate the two DMA channels.
DMA
Control
Logic
Adder Control
Logic
20-bit Adder/Subtractor
C8h-Transfer Counter Channel 0
C6h,C4h-Destination Address Channel 0
C2h,C0h-Source Address Channel 0
D8h-Transfer Counter Channel 1
D2h,D0h-Source Address Channel 1
D6h,D4h-Destination Address Channel 1
Request
Arbitration
Logic
INT
Interrupt Request
CAh.8-Channel 0
CAh.8-Channel 1
Channel Control Register1,DAh
Channel Control Register0,CAh
Internal Address/Data Bus
Timer 2 Request
DRQ0
DRQ1
TDRQ
CAH.4-Channel 0
DAH.4-Channel 1
20 bit
20 bit
16 bit
DMA Unit Block
Serial Port0
Serial Port1
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