
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
74
The Serial Port 0 Status Register provides information about the current status of the serial port 0.
Bit 15-11
: Reserved.
Bit 10: BRK1
, Long Break Detected. This bit should be reset by software.
When a long break is detected, this bit will be set high.
Bit 9 : BRK0
, Short Break Detected. This bit should be reset by software.
When a short break is detected, this bit will be set high
Bit 8: RB8,
Received Bit 8. This bit should be reset by software.
This bit contains the ninth data bit received in mode 2 and mode 3.
Bit 7: RDR,
Received Data Ready. Read only.
The Received Data Register contains valid data, this bit is set high. This bit can only be reset by reading the Serial
Port 0 Receive Register.
Bit 6: THRE
, Transmit Hold Register Empty. Read only.
When the Transmit Hold Register is ready to accept data, this bit will be set. This bit will be reset when writing data
to the Transmit Hold Register.
Bit 5: FER
, Framing Error detected. This bit should be reset by software.
This bit is set when a framing error is detected.
Bit 4: OER
, Overrun Error Detected. This bit should be reset by software.
This bit is set when an overrun error is detected.
Bit 3: PER
, Parity Error Detected. This bit should be reset by software.
This bit is set when a parity error ( for mode 1 and mode 3) is detected.
Bit 2: TEMT
, Transmitter Empty. This bit is read only.
When the Transmit Shift Register is empty, this bit will be set.
Bit 1: HS0
, Handshake Signal 0. This bit is read only.
This bit reflects the inverted value of the external
0
CTS pin.
Bit 0 :
Reserved.
Bit 15-8
: Reserved
Serial Port 0 Status Register
Offset : 82h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
BRK1
TEMT
HS0
Res
Reserved
BRK0
RB8
RDR THRE FER
OER
PER
Serial Port 0 Transmit Register
Offset : 84h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
TDATA