
R DC
9. System Clock Block
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
23
Bit 15
:
PSEN
, Enable Power-save Mode. This bit is cleared by hardware when an external interrupt occurs. This bit does not
be changed when software interrupts (INT instruction) and exceptions occurs.
Set 1: enable power-save mode and divides the internal operating clock by the value in F2-F0.
Bit14 : MCSBIT
,
MCS control bit. Set to 0: The
0
MCS operate normally. Set to 1:
0
MCS is active over the entire
MCSx range
Bit13-12
: Reserved
Bit 11
:
CBF
, CLKOUTB Output Frequency selection.
Set 1: CLKOUTB output frequency is same as crystal input frequency.
Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor
internal clock.
Bit 10 : CBD
, CLKOUTB Drive Disable
Set 1: Disable the CLKOUTB. This pin will be three-state.
Set 0 : Enable the CLKOUTB.
Bit 9: CAF
, CLKOUTA Output Frequency selection.
Set 1: CLKOUTA output frequency is same as crystal input frequency.
Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor
X1
X2
CLKIN
or
CLKIN/2
CLOCK
Divisior
(CLK/2-CLK/128)
MUX
CAF(F0h.9)
MUX
CBF(F0h.11)
CAD(F0h.8)
CBD(F0h.10)
F2-F0(F0h.2-F0h.0)
PSEN(F0h.15)
CLK
CLKIN
CLKIN/2 Select
S6/CLKDIV2
CLKOUTA
CLKOUTB
Microprocessor Internal Clock
System Clock
enable/disable
Divisor Select
Power-Save Control Register
Offset : F0h
Reset Value : 0000h
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
M
PSEN
0
0
0
0
0
F2
F1
F0
CAD
CAF
CBD
CBF
0
0