
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
48
Set 1: The corresponding DMA channel or INT has an interrupt pending.
Bit 1:
Reserved.
Bit 0 : TMR
, Timer Interrupt Request.
Set 1: The timer control unit has an interrupt pending.
(Slave Mode)
The Interrupt Request register is a read-only register. For internal interrupts (D1/I6, D0/I5, TMR2, TMR1, and TMR0), the
corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt
acknowledge.
Bit 15-6 :
Reserved.
Bit 5-4 :
TMR2/TMR1
, Timer2/Timer1 Interrupt Request.
Set 1: Indicates the state of any interrupt requests form the associated timer.
Bit 3-2 : D1/I6-D0/I5
, DMA Channel or INT Interrupt Request.
Set 1: Indicates the corresponding DMA channel or INT has an interrupt pending.
Bit 1 :
Reserved.
Bit 0 : TMR0
, Timer 0 Interrupt Request.
Set 1: Indicates the state of an interrupt request from Timer 0.
(Master Mode)
The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared
by writing the corresponding interrupt type to the EOI register.
Bit 15-11 :
Reserved.
Bit 10 : SP0
, Serial Port 0 Interrupt In-Service.
Set 1: the serial port 0 interrupt is currently being serviced.
Bit 9 : SP1
, Serial Port 1 Interrupt In-Service.
Set 1: the serial port 1 interrupt is currently being serviced.
In - Service Register
Offset : 2Ch
Reset Value : 0000h
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
D0/I5
Res
TMR
D1/I6
I0
I1
I2
I3
I4
SP1
SP0
Interrupt Request Register
Offset : 2Eh
Reset Value : 0000h
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
D0/I5
Res
TMR0
D1/I6
TMR1
TMR2